368 lines
14 KiB
Verilog
368 lines
14 KiB
Verilog
`timescale 1 ns / 1 ps
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module eeg_emg_upload
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(
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input clk ,
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input rst_n ,
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(*mark_debug="true"*)input [ 8-1:0] m_axis_eeg_tdata ,
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(*mark_debug="true"*)input m_axis_eeg_tlast ,
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(*mark_debug="true"*)input m_axis_eeg_tvalid ,
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(*mark_debug="true"*)input [ 8-1:0] m_axis_emg_tdata ,
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(*mark_debug="true"*)input m_axis_emg_tlast ,
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(*mark_debug="true"*)input m_axis_emg_tvalid ,
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(*mark_debug="true"*)input diff_pkt_data_sel ,
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(*mark_debug="true"*)input [1:0] eeg_emg_sel , // eeg_emg_sel[1]:emg,eeg_emg_sel[0]:eeg
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(*mark_debug="true"*)input [15:0] eeg_send_package_num ,
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(*mark_debug="true"*)input [15:0] emg_send_package_num ,
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input stop_sample ,
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(*mark_debug="true"*)output reg [7:0] eeg_emg_tdata ,
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(*mark_debug="true"*)output reg eeg_emg_tvalid ,
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(*mark_debug="true"*)output reg eeg_emg_tlast
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);
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(*mark_debug="true"*)reg [15:0] eeg_data_cnt ;
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(*mark_debug="true"*)wire [8:0] axis_emg_fifo_tdata ;
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(*mark_debug="true"*)reg fifo_emg_rd_en ;
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(*mark_debug="true"*)reg fifo_emg_rd_en_dly ;
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(*mark_debug="true"*)reg [15:0] fifo_rd_en_cnt ;
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(*mark_debug="true"*)wire [8:0] fifo_rd_data ;
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(*mark_debug="true"*)reg [7:0] axis_emg_tdata_tmp ;
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(*mark_debug="true"*)reg axis_emg_tlast_tmp ;
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(*mark_debug="true"*)reg axis_emg_tvalid_tmp ;
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(*mark_debug="true"*)reg [7:0] axis_eeg_tdata_tmp ;
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(*mark_debug="true"*)reg axis_eeg_tlast_tmp ;
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(*mark_debug="true"*)reg axis_eeg_tvalid_tmp ;
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(*mark_debug="true"*)reg [7:0] eeg_emg_tdata_tmp ;
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(*mark_debug="true"*)reg eeg_emg_tvalid_tmp ;
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(*mark_debug="true"*)reg eeg_emg_tlast_tmp ;
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(*mark_debug="true"*)wire [ 8-1:0] msg_crc[0:1] ;
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(*mark_debug="true"*)wire [16-1:0] crc16_out ;//wire
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(*mark_debug="true"*)reg [16-1:0] crc16 ;
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(*mark_debug="true"*)reg crc_vld ;
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(*mark_debug="true"*)reg fifo_rst ;
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assign axis_emg_fifo_tdata[8:0]={m_axis_emg_tlast,m_axis_emg_tdata[7:0]};
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assign crc16_out = crc16_d8(crc16, eeg_emg_tdata_tmp);
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always @(posedge clk or negedge rst_n) begin//eeg数据计数
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if (!rst_n) begin
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fifo_rst <= 1'b1 ;
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end else begin
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fifo_rst <= stop_sample ;
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end
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end
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always @(posedge clk or negedge rst_n) begin//eeg数据计数
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if (!rst_n) begin
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eeg_data_cnt[15:0] <= 16'b0 ;
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end else if(stop_sample)begin
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eeg_data_cnt[15:0] <= 16'b0 ;
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end else if(m_axis_eeg_tlast==1'b1)begin
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eeg_data_cnt[15:0] <= 16'b0 ;
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end else if(m_axis_eeg_tvalid==1'b1)begin
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eeg_data_cnt[15:0] <= eeg_data_cnt[15:0]+1'b1 ;
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end else begin
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eeg_data_cnt[15:0] <= eeg_data_cnt[15:0] ;
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end
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end
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always @(posedge clk or negedge rst_n) begin//emg 读使能打拍
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if (!rst_n) begin
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fifo_emg_rd_en_dly <= 1'b0 ;
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end else if(stop_sample)begin
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fifo_emg_rd_en_dly <= 1'b0 ;
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end else begin
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fifo_emg_rd_en_dly <= fifo_emg_rd_en ;
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end
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end
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always @(posedge clk or negedge rst_n) begin//emg读使能产生?当fifo_emg_rd_en为1和fifo_rd_en_cnt[15:0]为emg_send_package_num[15:0]-1时，需要将其置为0，其它则用fifo_emg_rd_en
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if (!rst_n) begin
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fifo_emg_rd_en <= 1'b0;
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end else if(stop_sample)begin
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fifo_emg_rd_en <= 1'b0;
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end else if(eeg_emg_sel[1:0]==2'b11)begin
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if(m_axis_eeg_tlast==1'b1)
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fifo_emg_rd_en <= 1'b1;
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else if((fifo_emg_rd_en == 1'b1)&&(fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-1))
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fifo_emg_rd_en <= 1'b0;
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else
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fifo_emg_rd_en <= fifo_emg_rd_en ;
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end else if(eeg_emg_sel[1:0]==2'b10)begin
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if(m_axis_emg_tlast==1'b1)
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fifo_emg_rd_en <= 1'b1;
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else if((fifo_emg_rd_en == 1'b1)&&(fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-1))
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fifo_emg_rd_en <= 1'b0;
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else
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fifo_emg_rd_en <= fifo_emg_rd_en ;
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end else begin
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fifo_emg_rd_en <= 1'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin//emg读使能计数?
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if (!rst_n) begin
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fifo_rd_en_cnt[15:0] <= 16'b0;
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end else if(stop_sample)begin
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fifo_rd_en_cnt[15:0] <= 16'b0;
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end else if(fifo_emg_rd_en==1'b1)begin
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fifo_rd_en_cnt[15:0] <= fifo_rd_en_cnt[15:0]+1'b1 ;
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end else begin
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fifo_rd_en_cnt[15:0] <= 16'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin//emg valid_tmp和tdata_tmp产生
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if (!rst_n) begin
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axis_emg_tvalid_tmp <= 1'b0 ;
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axis_emg_tdata_tmp[7:0] <= 8'b0 ;
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end else if(stop_sample)begin
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axis_emg_tvalid_tmp <= 1'b0 ;
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axis_emg_tdata_tmp[7:0] <= 8'b0 ;
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end else if(eeg_emg_sel[1:0]==2'b11)begin//当eeg和emg都有时?
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if(fifo_emg_rd_en_dly)begin
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if(fifo_rd_en_cnt[15:0] <= 16'd85)begin//去掉emg头
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axis_emg_tvalid_tmp <= 1'b0 ;
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axis_emg_tdata_tmp[7:0] <= fifo_rd_data[7:0] ;
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end else if(fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-16'd13)begin
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axis_emg_tdata_tmp[7:0] <= msg_crc[0][7:0];
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end else if(fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-16'd12)begin
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axis_emg_tdata_tmp[7:0] <= msg_crc[1][7:0];
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end else begin
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axis_emg_tvalid_tmp <= 1'b1 ;
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axis_emg_tdata_tmp[7:0] <= fifo_rd_data[7:0] ;
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end
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end else begin
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axis_emg_tvalid_tmp <= 1'b0 ;
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axis_emg_tdata_tmp[7:0] <= fifo_rd_data[7:0] ;
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end
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end else if(eeg_emg_sel[1:0]==2'b10)begin//当只有emg时?
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axis_emg_tvalid_tmp <= fifo_emg_rd_en_dly ;
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axis_emg_tdata_tmp[7:0] <= fifo_rd_data[7:0] ;
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end else begin
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axis_emg_tvalid_tmp <= 1'b0;
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axis_emg_tdata_tmp[7:0] <= 8'b0 ;
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end
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end
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always @(posedge clk or negedge rst_n) begin//emg tlast_tmp产生
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if (!rst_n)
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axis_emg_tlast_tmp <= 1'b0 ;
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else if(stop_sample)begin
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axis_emg_tlast_tmp <= 1'b0 ;
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end else if((eeg_emg_sel[1:0]==2'b11)||(eeg_emg_sel[1:0]==2'b10))begin//閲囬泦鏉垮拰emg閮芥湁鏃舵垨鑰呭彧鏈塭mg鏃?
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if((fifo_emg_rd_en==1'b0)&&(fifo_emg_rd_en_dly==1'b1))
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axis_emg_tlast_tmp <= 1'b1 ;
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else
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axis_emg_tlast_tmp <= 1'b0 ;
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end else begin
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axis_emg_tlast_tmp <= 1'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin//eeg valid_tmp和data_tmp[7:0]产生 ，根据选择来判断，2'b11来判断
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if (!rst_n) begin
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axis_eeg_tvalid_tmp <= 1'b0 ;
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axis_eeg_tdata_tmp[7:0] <= 8'b0 ;
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end else if(stop_sample)begin
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axis_eeg_tvalid_tmp <= 1'b0 ;
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axis_eeg_tdata_tmp[7:0] <= 8'b0 ;
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end else if(eeg_emg_sel[1:0]==2'b11)begin//当eeg和emg都有时?
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if(m_axis_eeg_tvalid)begin
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if(eeg_data_cnt[15:0] >= eeg_send_package_num[15:0]-16'd14)begin//去掉eeg的尾巴
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axis_eeg_tvalid_tmp <= 1'b0 ;
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axis_eeg_tdata_tmp[7:0] <= axis_eeg_tdata_tmp[7:0] ;
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end else begin
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axis_eeg_tvalid_tmp <= 1'b1 ;
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axis_eeg_tdata_tmp[7:0] <= m_axis_eeg_tdata[7:0] ;
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end
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end else begin
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axis_eeg_tvalid_tmp <= 1'b0 ;
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axis_eeg_tdata_tmp[7:0] <= m_axis_eeg_tdata[7:0] ;
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end
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end else if(eeg_emg_sel[1:0]==2'b01)begin//当只有eeg时?
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axis_eeg_tvalid_tmp <= m_axis_eeg_tvalid ;
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axis_eeg_tdata_tmp[7:0] <= m_axis_eeg_tdata[7:0] ;
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end else begin
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axis_eeg_tvalid_tmp <= 1'b0;
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axis_eeg_tdata_tmp[7:0] <= 8'b0 ;
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end
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end
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always @(posedge clk or negedge rst_n) begin//emg tlast_tmp产生,先用stop_sample，然后根据选择的sel来判断如何做
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if (!rst_n)
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axis_eeg_tlast_tmp <= 1'b0 ;
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else if(stop_sample)begin
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axis_eeg_tlast_tmp <= 1'b0 ;
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end else if(eeg_emg_sel[1:0]==2'b01)begin//当只有eeg时?
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axis_eeg_tlast_tmp <= m_axis_eeg_tlast ;
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end else begin
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axis_eeg_tlast_tmp <= 1'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin//emg valid_tmp和data_tmp[7:0]产生
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if (!rst_n) begin
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eeg_emg_tvalid_tmp <= 1'b0 ;
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eeg_emg_tdata_tmp[7:0] <= 8'b0 ;
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eeg_emg_tlast_tmp <= 1'b0 ;
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end else if(stop_sample)begin
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eeg_emg_tvalid_tmp <= 1'b0 ;
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eeg_emg_tdata_tmp[7:0] <= 8'b0 ;
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eeg_emg_tlast_tmp <= 1'b0 ;
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end else if(eeg_emg_sel[1:0]==2'b11)begin//当eeg和emg都有时?
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if(axis_eeg_tvalid_tmp==1'b1)begin
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eeg_emg_tvalid_tmp <= axis_eeg_tvalid_tmp ;
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eeg_emg_tdata_tmp[7:0] <= axis_eeg_tdata_tmp[7:0] ;
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eeg_emg_tlast_tmp <= axis_eeg_tlast_tmp ;
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end else if(axis_emg_tvalid_tmp==1'b1)begin
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eeg_emg_tvalid_tmp <= axis_emg_tvalid_tmp ;
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eeg_emg_tdata_tmp[7:0] <= axis_emg_tdata_tmp[7:0] ;
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eeg_emg_tlast_tmp <= axis_emg_tlast_tmp ;
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end else begin
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eeg_emg_tvalid_tmp <= 1'b0 ;
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eeg_emg_tdata_tmp[7:0] <= eeg_emg_tdata_tmp[7:0] ;
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eeg_emg_tlast_tmp <= 1'b0 ;
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end
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end else if(eeg_emg_sel[1:0]==2'b01)begin //当只有eeg时?
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eeg_emg_tvalid_tmp <= axis_eeg_tvalid_tmp ;
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eeg_emg_tdata_tmp[7:0] <= axis_eeg_tdata_tmp[7:0] ;
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eeg_emg_tlast_tmp <= axis_eeg_tlast_tmp ;
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end else if(eeg_emg_sel[1:0]==2'b10)begin//当只有emg时?
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eeg_emg_tvalid_tmp <= axis_emg_tvalid_tmp ;
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eeg_emg_tdata_tmp[7:0] <= axis_emg_tdata_tmp[7:0] ;
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eeg_emg_tlast_tmp <= axis_emg_tlast_tmp ;
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end else begin
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eeg_emg_tvalid_tmp <= 1'b0 ;
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eeg_emg_tdata_tmp[7:0] <= 8'b0 ;
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eeg_emg_tlast_tmp <= 1'b0 ;
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end
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end
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always @(posedge clk or negedge rst_n) begin//主要计算eeg_emng_tlast
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if (!rst_n) begin
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eeg_emg_tvalid <= 1'b0 ;
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eeg_emg_tlast <= 1'b0 ;
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end else if(stop_sample)begin
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eeg_emg_tvalid <= 1'b0 ;
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eeg_emg_tlast <= 1'b0 ;
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end else begin //打拍?
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eeg_emg_tvalid <= eeg_emg_tvalid_tmp ;
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eeg_emg_tlast <= eeg_emg_tlast_tmp ;
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end
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end
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always @(posedge clk or negedge rst_n) begin//
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if (!rst_n) begin
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eeg_emg_tdata[7:0] <= 8'b0 ;
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end else if(stop_sample)begin
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eeg_emg_tdata[7:0] <= 8'b0 ;
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end else if((eeg_emg_sel[1:0]==2'b11)&&(diff_pkt_data_sel==1'b0))begin //eeg和emg都有时? diff_pkt_data_sel==1'b0 默认差分打包数据 1：选择差分8通道原始数据
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if(eeg_emg_tvalid_tmp==1'b1)begin
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if(fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-16'd11)begin
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eeg_emg_tdata[7:0] <= msg_crc[0][7:0];
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end else if(fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-16'd10)begin
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eeg_emg_tdata[7:0] <= msg_crc[1][7:0];
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end else begin
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eeg_emg_tdata[7:0] <= eeg_emg_tdata_tmp[7:0] ;
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end
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end else begin
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eeg_emg_tdata[7:0] <= eeg_emg_tdata[7:0] ;
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end
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end else if(((eeg_emg_sel[1:0]==2'b10)&&(diff_pkt_data_sel==1'b0))||(eeg_emg_sel[1:0]==2'b01))begin
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eeg_emg_tdata[7:0] <= eeg_emg_tdata_tmp[7:0] ;
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end else begin
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eeg_emg_tdata[7:0] <= 8'b0 ;
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end
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end
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function automatic [15:0] crc16_d8;
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input [15:0] crcIn;
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input [7:0] data;
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begin
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crc16_d8[0] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ crcIn[8] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
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crc16_d8[1] = crcIn[9];
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crc16_d8[2] = crcIn[10];
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crc16_d8[3] = crcIn[11];
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crc16_d8[4] = crcIn[12];
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crc16_d8[5] = crcIn[13];
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crc16_d8[6] = crcIn[0] ^ crcIn[14] ^ data[0];
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crc16_d8[7] = crcIn[0] ^ crcIn[1] ^ crcIn[15] ^ data[0] ^ data[1];
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crc16_d8[8] = crcIn[1] ^ crcIn[2] ^ data[1] ^ data[2];
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crc16_d8[9] = crcIn[2] ^ crcIn[3] ^ data[2] ^ data[3];
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crc16_d8[10] = crcIn[3] ^ crcIn[4] ^ data[3] ^ data[4];
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crc16_d8[11] = crcIn[4] ^ crcIn[5] ^ data[4] ^ data[5];
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crc16_d8[12] = crcIn[5] ^ crcIn[6] ^ data[5] ^ data[6];
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crc16_d8[13] = crcIn[6] ^ crcIn[7] ^ data[6] ^ data[7];
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crc16_d8[14] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6];
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crc16_d8[15] = crcIn[0] ^ crcIn[1] ^ crcIn[2] ^ crcIn[3] ^ crcIn[4] ^ crcIn[5] ^ crcIn[6] ^ crcIn[7] ^ data[0] ^ data[1] ^ data[2] ^ data[3] ^ data[4] ^ data[5] ^ data[6] ^ data[7];
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end
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endfunction
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always @ (posedge clk or negedge rst_n) begin//主要计算crc_vld
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if (!rst_n)begin
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crc_vld <= 1'b0;
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end else if(stop_sample==1'b1)begin
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crc_vld <= 1'b0;
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end else if (eeg_emg_tlast_tmp==1'b1)begin
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crc_vld <= 1'b0;
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end else if(axis_eeg_tvalid_tmp | axis_emg_tvalid_tmp)begin//axis_record_tvalid_tmp==1'b1
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crc_vld <= 1'b1;
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end else begin
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crc_vld <= crc_vld;
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end
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end
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always @ (posedge clk or negedge rst_n) begin//主要计算crc16
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if (!rst_n)begin
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crc16 <= 16'hFFFF;
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end else if(stop_sample==1'b1)begin
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crc16 <= 16'hFFFF;
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end else if (crc_vld==1'b0)begin
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crc16 <= 16'hFFFF;
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end else if(eeg_emg_sel[1:0]==2'b01)begin//当只有eeg时?
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if(eeg_emg_tvalid_tmp==1'b1)begin
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if((eeg_data_cnt[15:0] == eeg_send_package_num[15:0]-16'd14)||(eeg_data_cnt[15:0] == eeg_send_package_num[15:0]-16'd13))begin
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crc16 <= crc16 ;
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end else begin
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crc16 <= crc16_out ;
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end
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end else begin
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crc16 <= crc16;//crc16_out ;
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end
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end else if((eeg_emg_sel[1:0]==2'b11)||(eeg_emg_sel[1:0]==2'b10))begin//eeg和emg都有时或者只有emg时?
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if(eeg_emg_tvalid_tmp==1'b1)begin
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if((fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-16'd11)||(fifo_rd_en_cnt[15:0]==emg_send_package_num[15:0]-16'd10))begin
|
|
crc16 <= crc16 ;
|
|
end else begin
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|
crc16 <= crc16_out ;
|
|
end
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end else begin
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|
crc16 <= crc16;//crc16_out ;
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|
end
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|
end else begin//
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|
crc16 <= crc16_out ;
|
|
end
|
|
end
|
|
|
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assign msg_crc[0] = crc16[15: 8];
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assign msg_crc[1] = crc16[ 7: 0];
|
|
|
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fifo_generator_0 u0_fifo_generator_0(
|
|
.full ( ),
|
|
.din (axis_emg_fifo_tdata[8:0]),
|
|
.wr_en (m_axis_emg_tvalid ),
|
|
.empty ( ),
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|
.dout (fifo_rd_data[8:0] ),
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|
.rd_en (fifo_emg_rd_en ),
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|
.rst (fifo_rst ),//~rst_n(20260902 change)
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|
.wr_clk(clk ),
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|
.rd_clk(clk )
|
|
);
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|
|
|
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endmodule
|