76 lines
1.9 KiB
Verilog
76 lines
1.9 KiB
Verilog
`timescale 1ns/1ps
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module trigger_top_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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localparam T_CLK = 10 ; //ns
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localparam DATA_WIDTH = 64 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [32-1:0] trigger_in_int ;
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reg [32-1:0] trigger_in_ext ;
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wire [32-1:0] trigger_tdata ;
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wire trigger_tvalid ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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trigger_top#
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(
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.CLK_PERIOD ( T_CLK )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.trigger_in_int ( trigger_in_int ),
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.trigger_in_ext ( trigger_in_ext ),
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.trigger_tdata ( trigger_tdata ),
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.trigger_tvalid ( trigger_tvalid )
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);
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#100
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while (1) begin
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trigger_in_ext <= trigger_in_ext + 1'b1;
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#80_060;
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trigger_in_int <= trigger_in_int + 1'b1;
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#20_000;
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end
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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trigger_in_int <= 32'h123;
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trigger_in_ext <= 0;
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end
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endtask
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endmodule |