364 lines
11 KiB
Verilog
364 lines
11 KiB
Verilog
`timescale 1 ns / 1 ps
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module transmit_config#
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(
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parameter CHIPSET_QTY = 4
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output reg [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output reg [CHIPSET_QTY-1:0] stim_en ,
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output reg [32-1:0] update_period ,
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output reg enable_timer ,
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output reg dds_by_ps ,
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output reg dds_aclken ,
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output dds_aresetn ,
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output reg sw_enable ,
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output reg sw_data_sel ,
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output reg [64-1:0] sw_data_0 ,
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input [64-1:0] sw_state ,
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output [ 8*16*CHIPSET_QTY-1:0] stim_trim_p_array_array ,
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output [ 8*16*CHIPSET_QTY-1:0] stim_trim_n_array_array ,
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output reg phase_enable ,
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output [32*16-1:0] phase_inc_array ,
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output [32*16-1:0] phase_off_array ,
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input [64-1:0] stim_monitor_rt ,
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input [64-1:0] stim_monitor_latch ,
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output [ 1*CHIPSET_QTY-1:0] spi_cmd_valid_array ,
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output [32*CHIPSET_QTY-1:0] spi_cmd_data_array ,
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input [ 1*CHIPSET_QTY-1:0] spi_cmd_ready_array ,
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input [ 1*CHIPSET_QTY-1:0] spi_res_en_array ,
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input [32*CHIPSET_QTY-1:0] spi_res_array
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam BRAM_ADDR_TEST_RW = 13'h0000;
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localparam BRAM_ADDR_TEST_RO_DATA = 13'h0004;
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localparam BRAM_ADDR_STIM_ENABLE = 13'h0010;
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localparam BRAM_ADDR_UPDATE_PERIOD = 13'h0020;
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localparam BRAM_ADDR_UPLOAD_ROUND_NUM = 13'h0024; //Unused
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localparam BRAM_ADDR_ENABLE = 13'h0028;
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localparam BRAM_ADDR_DDS_CTRL = 13'h002C;
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localparam BRAM_ADDR_DDS_PHASE_TRIG = 13'h0030; //Unused
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localparam BRAM_ADDR_SWITCH_CTRL = 13'h0034;
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localparam BRAM_ADDR_SWITCH_DATA0 = 13'h0040;
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localparam BRAM_ADDR_SWITCH_DATA1 = 13'h0044;
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localparam BRAM_ADDR_CUR_MON_RESET = 13'h0048; //Unused
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localparam BRAM_ADDR_CUR_MON_STATE0 = 13'h0050;
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localparam BRAM_ADDR_CUR_MON_STATE1 = 13'h0054;
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localparam BRAM_ADDR_CUR_MON_LATCH0 = 13'h0060;
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localparam BRAM_ADDR_CUR_MON_LATCH1 = 13'h0064;
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localparam BRAM_ADDR_SPI_STATE_MASK = 13'h1F80;
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localparam BRAM_ADDR_SPI_STATE_START = 13'h0100;
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localparam BRAM_ADDR_SPI_TX_MASK = 13'h1F80;
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localparam BRAM_ADDR_SPI_TX_START = 13'h0180;
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localparam BRAM_ADDR_SPI_RX_MASK = 13'h1F80;
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localparam BRAM_ADDR_SPI_RX_START = 13'h0200;
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localparam BRAM_ADDR_SPI_ERR_MASK = 13'h1F80;
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localparam BRAM_ADDR_SPI_ERR_START = 13'h0280;
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localparam BRAM_ADDR_DDS_PHASE_INC_MASK = 13'h1F80;
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localparam BRAM_ADDR_DDS_PHASE_INC_START = 13'h0400;
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localparam BRAM_ADDR_DDS_PHASE_OFF_MASK = 13'h1F80;
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localparam BRAM_ADDR_DDS_PHASE_OFF_START = 13'h0480;
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localparam BRAM_ADDR_STIM_TRIM_P_MASK = 13'h1F00;
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localparam BRAM_ADDR_STIM_TRIM_P_START = 13'h0600;
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localparam BRAM_ADDR_STIM_TRIM_N_MASK = 13'h1F00;
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localparam BRAM_ADDR_STIM_TRIM_N_START = 13'h0700;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [32-1:0] test_data ;
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wire bram_wr_valid ;
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wire bram_rd_valid ;
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reg [32-1:0] spi_state_r[0:CHIPSET_QTY-1] ;
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reg dds_areset ;
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reg [32-1:0] spi_cmd_data[0:CHIPSET_QTY-1] ;
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reg spi_cmd_valid[0:CHIPSET_QTY-1] ;
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wire spi_cmd_ready[0:CHIPSET_QTY-1] ;
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wire spi_res_en[0:CHIPSET_QTY-1] ;
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wire [32-1:0] spi_res[0:CHIPSET_QTY-1] ;
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reg [32-1:0] spi_res_r[0:CHIPSET_QTY-1] ;
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reg [ 8-1:0] stim_trim_p[0:16*CHIPSET_QTY-1] ;
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reg [ 8-1:0] stim_trim_n[0:16*CHIPSET_QTY-1] ;
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reg [32-1:0] dds_phase_inc[0:16-1] ;
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reg [32-1:0] dds_phase_off[0:16-1] ;
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reg [32-1:0] unknow_data ;
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reg [ 5-1:0] spi_cmd_chip ;
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integer n;
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genvar i;
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genvar j;
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//*****************************************************************************
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// Procedural blocks
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//*****************************************************************************
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : spi_state
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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spi_state_r[i] <= 0;
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end else if ( spi_res_en[i] ) begin
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spi_state_r[i][0] <= spi_state_r[i][0] | spi_res_en[i];
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end else if ( (bram_addr & BRAM_ADDR_SPI_STATE_MASK) == BRAM_ADDR_SPI_STATE_START ) begin
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if (bram_addr[6:2]==i)
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spi_state_r[i] <= 0;
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end
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end
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : spi_rx
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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spi_res_r[i] <= 0;
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else if ( spi_res_en[i] )
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spi_res_r[i] <= spi_res[i];
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end
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end
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endgenerate
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//write bram/Set config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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stim_en <= 1'b0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_STIM_ENABLE ) )
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stim_en <= bram_din[CHIPSET_QTY-1:0];
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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n = 0;
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while(n<16) begin
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dds_phase_inc[n] <= 32'h0015493D;//3kHz: 32'h003EEA21, 10kHz: 32'h00D1B717
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n = n + 1;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_DDS_PHASE_INC_MASK) == BRAM_ADDR_DDS_PHASE_INC_START ) )
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dds_phase_inc[bram_addr[6:2]] <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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n = 0;
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while(n<16) begin
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dds_phase_off[n] <= 0;
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n = n + 1;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_DDS_PHASE_OFF_MASK) == BRAM_ADDR_DDS_PHASE_OFF_START ) )
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dds_phase_off[bram_addr[6:2]] <= bram_din;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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n = 0;
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while(n<16*CHIPSET_QTY) begin
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stim_trim_p[n] <= 8'h80;
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n = n + 1;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_STIM_TRIM_P_MASK) == BRAM_ADDR_STIM_TRIM_P_START ) ) begin
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stim_trim_p[(bram_addr[7:2]<<2)+0] <= bram_din[ 7: 0];
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stim_trim_p[(bram_addr[7:2]<<2)+1] <= bram_din[15: 8];
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stim_trim_p[(bram_addr[7:2]<<2)+2] <= bram_din[23:16];
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stim_trim_p[(bram_addr[7:2]<<2)+3] <= bram_din[31:24];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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n = 0;
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while(n<16*CHIPSET_QTY) begin
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stim_trim_n[n] <= 8'h80;
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n = n + 1;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_STIM_TRIM_N_MASK) == BRAM_ADDR_STIM_TRIM_N_START ) )begin
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stim_trim_n[(bram_addr[7:2]<<2)+0] <= bram_din[ 7: 0];
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stim_trim_n[(bram_addr[7:2]<<2)+1] <= bram_din[15: 8];
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stim_trim_n[(bram_addr[7:2]<<2)+2] <= bram_din[23:16];
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stim_trim_n[(bram_addr[7:2]<<2)+3] <= bram_din[31:24];
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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spi_cmd_chip <= 0;
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n = 0;
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while(n<CHIPSET_QTY) begin
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spi_cmd_data[n] <= 0;
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spi_cmd_valid[n] <= 1'b0;
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n = n + 1;
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end
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end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_SPI_TX_MASK) == BRAM_ADDR_SPI_TX_START ) ) begin
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spi_cmd_data[bram_addr[6:2]] <= bram_din;
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spi_cmd_valid[bram_addr[6:2]] <= 1'b1;
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spi_cmd_chip <= bram_addr[6:2];
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end else if ( spi_cmd_valid[spi_cmd_chip] && spi_cmd_ready[spi_cmd_chip] ) begin
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spi_cmd_valid[spi_cmd_chip] <= 1'b0;
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end
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end
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//write bram/Set config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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test_data <= 0;
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update_period <= 0;
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enable_timer <= 1'b0;
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dds_by_ps <= 1'b1;
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dds_aclken <= 1'b0;
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dds_areset <= 1'b0;
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phase_enable <= 1'b0;
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sw_enable <= 1'b0;
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sw_data_sel <= 1'b0;
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sw_data_0 <= 0;
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end else if ( bram_en && (bram_we == 4'hF) ) begin
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case ( bram_addr[12:0] )
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BRAM_ADDR_TEST_RW : test_data <= bram_din;
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BRAM_ADDR_UPDATE_PERIOD : update_period <= bram_din;
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BRAM_ADDR_ENABLE : enable_timer <= bram_din[0];
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BRAM_ADDR_DDS_CTRL : begin
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phase_enable <= bram_din[3];
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dds_areset <= bram_din[2];
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dds_aclken <= bram_din[1];
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dds_by_ps <= bram_din[0];
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end
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BRAM_ADDR_SWITCH_CTRL : begin
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sw_enable <= bram_din[0];
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sw_data_sel <= bram_din[1];
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end
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BRAM_ADDR_SWITCH_DATA0 : sw_data_0[31: 0]<= bram_din;
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BRAM_ADDR_SWITCH_DATA1 : sw_data_0[63:32]<= bram_din;
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default:
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unknow_data <= bram_din;
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endcase
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end else begin
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phase_enable <= 1'b0;
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dds_areset <= 1'b0;
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end
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end
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//read bram/Get config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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bram_dout <= 0;
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else if ( bram_en && (bram_we == 4'h0) ) begin
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case ( bram_addr[12:0] )
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BRAM_ADDR_TEST_RW : bram_dout <= test_data;
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BRAM_ADDR_TEST_RO_DATA : bram_dout <= 32'h12345678;
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BRAM_ADDR_UPDATE_PERIOD : bram_dout <= update_period;
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BRAM_ADDR_ENABLE : bram_dout <= {{31{1'b0}}, enable_timer};
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BRAM_ADDR_DDS_CTRL : bram_dout <= {{29{1'b0}}, dds_areset, dds_aclken, dds_by_ps};
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BRAM_ADDR_SWITCH_CTRL : bram_dout <= {{30{1'b0}}, sw_data_sel, sw_enable};
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BRAM_ADDR_SWITCH_DATA0 : bram_dout <= sw_state[31: 0];
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BRAM_ADDR_SWITCH_DATA1 : bram_dout <= sw_state[63:32];
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BRAM_ADDR_CUR_MON_STATE0 : bram_dout <= stim_monitor_rt[31: 0];
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BRAM_ADDR_CUR_MON_STATE1 : bram_dout <= stim_monitor_rt[63:32];
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BRAM_ADDR_CUR_MON_LATCH0 : bram_dout <= stim_monitor_latch[31: 0];
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BRAM_ADDR_CUR_MON_LATCH1 : bram_dout <= stim_monitor_latch[63:32];
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default: bram_dout <= 0;
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endcase
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if ( (bram_addr & BRAM_ADDR_SPI_STATE_MASK) == BRAM_ADDR_SPI_STATE_START )
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bram_dout <= spi_state_r[bram_addr[6:2]];
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if ( (bram_addr & BRAM_ADDR_SPI_RX_MASK) == BRAM_ADDR_SPI_RX_START )
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bram_dout <= spi_res_r[bram_addr[6:2]];
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end
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end
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//*****************************************************************************
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// Continuous assignments
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//*****************************************************************************
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assign bram_wr_valid = bram_en && (bram_we == 4'hF);
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assign bram_rd_valid = bram_en && (bram_we == 4'h0);
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assign dds_aresetn = ~dds_areset;
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack
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assign spi_cmd_valid_array[i] = spi_cmd_valid[i];
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assign spi_cmd_data_array[32*i+31 : 32*i] = spi_cmd_data[i];
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
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assign spi_cmd_ready[i] = spi_cmd_ready_array[i];
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack_trim_p
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for(j=0;j<16;j=j+1) begin : pack
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assign stim_trim_p_array_array[8*(16*i+j)+7 : 8*(16*i+j)] = stim_trim_p[16*i+j];
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end
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack_trim_n
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for(j=0;j<16;j=j+1) begin : pack
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assign stim_trim_n_array_array[8*(16*i+j)+7 : 8*(16*i+j)] = stim_trim_n[16*i+j];
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end
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end
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endgenerate
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generate
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for(i=0;i<16;i=i+1) begin : pack_dds
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assign phase_inc_array[32*i+31 : 32*i] = dds_phase_inc[i];
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assign phase_off_array[32*i+31 : 32*i] = dds_phase_off[i];
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end
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endgenerate
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack_res
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assign spi_res_en[i] = spi_res_en_array[i];
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assign spi_res[i] = spi_res_array[32*i+31 : 32*i];
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end
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endgenerate
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endmodule
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