223 lines
6.4 KiB
Verilog
223 lines
6.4 KiB
Verilog
`timescale 1 ns / 1 ps
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module trans_arrange#
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(
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parameter CMD_CNV = 2'b00,
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parameter CMD_EXTEND = 2'b01,
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parameter CMD_WRITE = 2'b10,
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parameter CMD_READ = 2'b11,
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parameter REG_ADDR_STIM_POL = 8'd44 ,
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parameter REG_ADDR_POS_CUR = 8'd64 ,
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parameter REG_ADDR_NEG_CUR = 8'd96
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)
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(
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input clk ,
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input rst_n ,
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input [16* 8-1:0] stim_trim_p_array ,
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input [16* 8-1:0] stim_trim_n_array ,
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input [16*9-1:0] sine_wave_array ,
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input trans_round ,
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//-------------------------------------------------- input
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input [ 32-1:0] s_axi_cmd_tdata ,
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input s_axi_cmd_tlast ,
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output reg s_axi_cmd_tready ,
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input s_axi_cmd_tvalid ,
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//-------------------------------------------------- output
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output reg [ 32-1:0] m_axi_trans_tdata ,
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output reg m_axi_trans_tlast ,
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input m_axi_trans_tready ,
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output reg m_axi_trans_tvalid
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam RX_ST = 4'd0 ;
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localparam DECODE_ST = 4'd1 ;
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localparam FILL_ST = 4'd2 ;
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localparam POL_ST = 4'd3 ;
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localparam SEND_ST = 4'd4 ;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [ 4-1:0] cstate ;
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reg [ 4-1:0] nstate ;
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wire [ 9-1:0] sine_wave[0:15] ;
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wire [ 8-1:0] stim_trim_p[0:15] ;
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wire [ 8-1:0] stim_trim_n[0:15] ;
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reg [32-1:0] stim_rx ;
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reg is_tlast ;
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reg ce ;
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reg [16-1:0] polarity_mark ;
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wire is_pol_cmd ;
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wire is_empty_cmd ;
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wire is_stim_cmd ;
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wire is_sine ;
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wire cnv_is_cover ;
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wire [ 4-1:0] stim_ch ;
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wire [ 7-1:0] sine_ch ;
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wire [ 9-1:0] gain_c ;
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wire [ 9-1:0] stim_data ;
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wire [ 8-1:0] stim_abs ;
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wire [ 8-1:0] magnitude ;
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wire stim_pol ;
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wire [ 8-1:0] stim_mag ;
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wire [ 8-1:0] current_trim ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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mult_gen_au8_bu9_p8 u_mult_gain
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(
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.CLK ( clk ),
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.A ( stim_abs ), // input wire [7: 0] A
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.B ( gain_c ), // input wire [8: 0] B
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.CE ( ce ),
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.P ( magnitude ) // output wire [7: 0] P
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);
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//*****************************************************************************
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always@( posedge clk or negedge rst_n ) begin
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if( !rst_n ) cstate <= RX_ST;
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else cstate <= nstate;
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end
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always@( * ) begin
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case ( cstate )
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RX_ST:
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if ( s_axi_cmd_tready && s_axi_cmd_tvalid )
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nstate <= DECODE_ST;
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else
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nstate <= RX_ST;
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DECODE_ST:
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if ( is_stim_cmd )
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nstate <= FILL_ST;
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else if ( is_pol_cmd )
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nstate <= POL_ST;
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else
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nstate <= SEND_ST;
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FILL_ST:
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nstate <= SEND_ST;
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POL_ST:
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nstate <= SEND_ST;
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SEND_ST:
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if ( m_axi_trans_tready && m_axi_trans_tvalid )
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nstate <= RX_ST;
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else
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nstate <= SEND_ST;
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default:
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nstate <= RX_ST;
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endcase
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end
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//reve
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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s_axi_cmd_tready <= 1'b0;
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else if ( nstate == RX_ST )
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s_axi_cmd_tready <= 1'b1;
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else
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s_axi_cmd_tready <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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stim_rx <= 0;
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is_tlast <= 1'b0;
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end else if ( s_axi_cmd_tready && s_axi_cmd_tvalid ) begin
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stim_rx <= s_axi_cmd_tdata;
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is_tlast <= s_axi_cmd_tlast;
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end
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end
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//stim
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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polarity_mark <= 0;
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else if ( trans_round )
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polarity_mark <= 0;
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else if ( (cstate == FILL_ST) && stim_pol)
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polarity_mark <= polarity_mark | (16'h0001 << stim_ch);
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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ce <= 1'b0;
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else if ( cstate == RX_ST && nstate == DECODE_ST )
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ce <= 1'b1;
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else
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ce <= 1'b0;
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end
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//transmit
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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m_axi_trans_tvalid <= 1'b0;
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m_axi_trans_tdata <= 0;
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m_axi_trans_tlast <= 1'b0;
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end else if ( m_axi_trans_tready && m_axi_trans_tvalid ) begin
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m_axi_trans_tvalid <= 1'b0;
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end else if ( nstate == SEND_ST && cstate == DECODE_ST ) begin
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m_axi_trans_tvalid <= 1'b1;
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m_axi_trans_tdata <= (is_empty_cmd)? 32'h40000000 : stim_rx;
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m_axi_trans_tlast <= is_tlast;
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end else if ( nstate == SEND_ST && cstate == FILL_ST ) begin
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m_axi_trans_tvalid <= 1'b1;
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m_axi_trans_tdata <= {2'b01, 2'b00, 1'b0, stim_pol, cnv_is_cover, 1'b1, stim_rx[23:16], current_trim, stim_mag};
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m_axi_trans_tlast <= is_tlast;
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end else if ( nstate == SEND_ST && cstate == POL_ST ) begin
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m_axi_trans_tvalid <= 1'b1;
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m_axi_trans_tdata <= {2'b10, stim_rx[29:24], REG_ADDR_STIM_POL, stim_rx[15:0] | polarity_mark};
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m_axi_trans_tlast <= is_tlast;
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end
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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genvar i;
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generate
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for(i=0;i<16;i=i+1) begin : unpack
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assign sine_wave[i] = sine_wave_array[9*i+8 : 9*i];
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end
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endgenerate
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generate
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for(i=0;i<16;i=i+1) begin : unpack_trim
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assign stim_trim_p[i] = stim_trim_p_array[8*i+7 : 8*i];
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assign stim_trim_n[i] = stim_trim_n_array[8*i+7 : 8*i];
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end
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endgenerate
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assign is_pol_cmd = (stim_rx[31:30]==CMD_WRITE && stim_rx[23:16]==REG_ADDR_STIM_POL)? 1'b1:1'b0;
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assign is_empty_cmd = (stim_rx[31:30]==CMD_EXTEND && stim_rx[23:20]==4'h0)? 1'b1:1'b0;
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assign is_stim_cmd = (stim_rx[31:30]==CMD_EXTEND && stim_rx[23:20]!=4'h0)? 1'b1:1'b0;
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assign is_sine = (stim_rx[31:30]==CMD_EXTEND && stim_rx[29]==1'b0)? 1'b1:1'b0;
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assign cnv_is_cover = (stim_rx[31:30]==CMD_EXTEND && stim_rx[28]==1'b1)? 1'b1:1'b0;
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assign stim_ch = stim_rx[19:16];
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assign sine_ch = stim_rx[15: 9];
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assign gain_c = stim_rx[ 8: 0];
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assign stim_data = sine_wave[sine_ch];
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assign stim_abs = stim_data[7:0];
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assign stim_pol = (is_sine)? (~stim_data[8]):stim_rx[8];
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assign stim_mag = (is_sine)? magnitude:stim_rx[7:0];
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assign current_trim = stim_pol? (stim_trim_p[stim_ch]):(stim_trim_n[stim_ch]);
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endmodule
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