316 lines
7.7 KiB
Verilog
316 lines
7.7 KiB
Verilog
`timescale 1ns/1ps
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module sine_gen_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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parameter T_CLK = 10; //ns
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg enable_timer ;
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reg [32-1:0] update_period ;
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wire trans_round ;
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wire trans_pulse ;
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reg aclken ;
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reg areset ;
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wire aresetn ;
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reg phase_enable ;
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reg [32-1:0] phase_inc[0:16-1] ;
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reg [32-1:0] phase_off[0:16-1] ;
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wire [32*16-1:0] phase_inc_array ;
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wire [32*16-1:0] phase_off_array ;
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wire [ 9*16-1:0] sine_wave_array ;
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wire [ 9-1:0] wave_data[0:16-1] ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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trans_timer u_trans_timer
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( enable_timer ),
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.update_period ( update_period ),
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.update ( trans_round ),
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.trans ( trans_pulse )
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);
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sine_gen DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.aclken ( aclken ),
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.aresetn ( aresetn ),
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.phase_enable ( phase_enable ),
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.phase_inc_array ( phase_inc_array ),
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.phase_off_array ( phase_off_array ),
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.update ( trans_round ),
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.sine_wave_array ( sine_wave_array )
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);
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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//aclken
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#600_000;
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@ ( posedge clk ) aclken <= 1'b1;
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#600_000;
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@ ( posedge clk ) aclken <= 1'b0;
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//aclken
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#600_000;
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@ ( posedge clk ) aclken <= 1'b1;
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#600_000;
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@ ( posedge clk ) aclken <= 1'b0;
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//areset
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#600_000;
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@ ( posedge clk ) areset <= 1'b1;
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#600_000;
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@ ( posedge clk ) areset <= 1'b0;
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//aclken
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#600_000;
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@ ( posedge clk ) aclken <= 1'b1;
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//areset
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#600_000;
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@ ( posedge clk ) areset <= 1'b1;
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//areset
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#600_000;
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@ ( posedge clk ) areset <= 1'b0;
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//aclken and areset
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#600_000;
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@ ( posedge clk ) aclken <= 1'b0;
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#600_000;
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@ ( posedge clk )
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phase_inc[ 0] = 32'h000A7C5B;
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phase_inc[ 1] = 32'h000FBA88;
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phase_inc[ 2] = 32'h0014F8B5;
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phase_inc[ 3] = 32'h001A36E3;
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phase_inc[ 4] = 32'h001F7510;
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phase_inc[ 5] = 32'h0024B33E;
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phase_inc[ 6] = 32'h0029F16B;
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phase_inc[ 7] = 32'h002F2F98;
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phase_inc[ 8] = 32'h003F2F98;
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phase_inc[ 9] = 32'h004F2F98;
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phase_inc[10] = 32'h005F2F98;
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phase_inc[11] = 32'h006F2F98;
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phase_inc[12] = 32'h007F2F98;
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phase_inc[13] = 32'h008F2F98;
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phase_inc[14] = 32'h009F2F98;
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phase_inc[15] = 32'h00AF2F98;
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@ ( posedge clk ) phase_enable <= 1'b1;
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@ ( posedge clk ) phase_enable <= 1'b0;
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//aclken and areset
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#600_000;
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@ ( posedge clk ) areset <= 1'b0;
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@ ( posedge clk ) aclken <= 1'b1;
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//aclken and areset
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#600_000;
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@ ( posedge clk ) aclken <= 1'b0;
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@ ( posedge clk ) areset <= 1'b1;
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#600_000;
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@ ( posedge clk )
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phase_inc[ 0] = 32'h000A7C5B;
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phase_inc[ 1] = 32'h000FBA88;
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phase_inc[ 2] = 32'h0014F8B5;
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phase_inc[ 3] = 32'h001A36E3;
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phase_inc[ 4] = 32'h001F7510;
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phase_inc[ 5] = 32'h0024B33E;
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phase_inc[ 6] = 32'h0029F16B;
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phase_inc[ 7] = 32'h002F2F98;
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phase_inc[ 8] = 32'h003F2F98;
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phase_inc[ 9] = 32'h004F2F98;
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phase_inc[10] = 32'h005F2F98;
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phase_inc[11] = 32'h006F2F98;
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phase_inc[12] = 32'h007F2F98;
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phase_inc[13] = 32'h008F2F98;
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phase_inc[14] = 32'h009F2F98;
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phase_inc[15] = 32'h00AF2F98;
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@ ( posedge clk ) phase_enable <= 1'b1;
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@ ( posedge clk ) phase_enable <= 1'b0;
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//aclken and areset
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#600_000;
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@ ( posedge clk ) aclken <= 1'b1;
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@ ( posedge clk ) areset <= 1'b0;
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//aclken and areset
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#600_000;
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@ ( posedge clk ) aclken <= 1'b1;
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@ ( posedge clk ) areset <= 1'b1;
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#600_000;
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@ ( posedge clk )
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phase_inc[ 0] = 32'h000A7C5B;
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phase_inc[ 1] = 32'h000FBA88;
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phase_inc[ 2] = 32'h0014F8B5;
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phase_inc[ 3] = 32'h001A36E3;
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phase_inc[ 4] = 32'h001F7510;
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phase_inc[ 5] = 32'h0024B33E;
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phase_inc[ 6] = 32'h0029F16B;
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phase_inc[ 7] = 32'h002F2F98;
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phase_inc[ 8] = 32'h003F2F98;
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phase_inc[ 9] = 32'h004F2F98;
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phase_inc[10] = 32'h005F2F98;
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phase_inc[11] = 32'h006F2F98;
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phase_inc[12] = 32'h007F2F98;
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phase_inc[13] = 32'h008F2F98;
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phase_inc[14] = 32'h009F2F98;
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phase_inc[15] = 32'h00AF2F98;
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@ ( posedge clk ) phase_enable <= 1'b1;
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@ ( posedge clk ) phase_enable <= 1'b0;
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//aclken and areset
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#600_000;
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@ ( posedge clk ) areset <= 1'b0;
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#600_000;
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@ ( posedge clk )
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phase_inc[ 0] = 32'h000A7C5B;
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phase_inc[ 1] = 32'h000FBA88;
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phase_inc[ 2] = 32'h0014F8B5;
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phase_inc[ 3] = 32'h001A36E3;
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phase_inc[ 4] = 32'h001F7510;
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phase_inc[ 5] = 32'h0024B33E;
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phase_inc[ 6] = 32'h0029F16B;
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phase_inc[ 7] = 32'h002F2F98;
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phase_inc[ 8] = 32'h003F2F98;
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phase_inc[ 9] = 32'h004F2F98;
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phase_inc[10] = 32'h005F2F98;
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phase_inc[11] = 32'h006F2F98;
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phase_inc[12] = 32'h007F2F98;
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phase_inc[13] = 32'h008F2F98;
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phase_inc[14] = 32'h009F2F98;
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phase_inc[15] = 32'h00AF2F98;
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@ ( posedge clk ) phase_enable <= 1'b1;
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@ ( posedge clk ) phase_enable <= 1'b0;
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#4_000_000;
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@ ( posedge clk ) aclken <= 1'b0;
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@ ( posedge clk ) areset <= 1'b1;
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#600_000;
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@ ( posedge clk ) aclken <= 1'b1;
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@ ( posedge clk ) areset <= 1'b0;
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#3_900_000;
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@ ( posedge clk ) areset <= 1'b1;
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#600_000;
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@ ( posedge clk ) areset <= 1'b0;
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#10_000_000;
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$stop;
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#600_000;
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@ ( posedge clk ) enable_timer <= 1'b1;
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#600_000;
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$stop;
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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enable_timer <= 1'b0 ;
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update_period <= 5_000/10 ; //30_000 ns
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aclken <= 1'b0 ;
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areset <= 1'b0 ;
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phase_enable <= 8'd0 ;
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phase_inc[ 0] = 32'h00000000;
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phase_inc[ 1] = 32'h00000000;
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phase_inc[ 2] = 32'h00000000;
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phase_inc[ 3] = 32'h00000000;
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phase_inc[ 4] = 32'h00000000;
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phase_inc[ 5] = 32'h00000000;
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phase_inc[ 6] = 32'h00000000;
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phase_inc[ 7] = 32'h00000000;
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phase_inc[ 8] = 32'h00000000;
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phase_inc[ 9] = 32'h00000000;
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phase_inc[10] = 32'h00000000;
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phase_inc[11] = 32'h00000000;
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phase_inc[12] = 32'h00000000;
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phase_inc[13] = 32'h00000000;
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phase_inc[14] = 32'h00000000;
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phase_inc[15] = 32'h00000000;
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phase_off[ 0] = 32'h00000000;
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phase_off[ 1] = 32'h00100000;
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phase_off[ 2] = 32'h00200000;
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phase_off[ 3] = 32'h00300000;
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phase_off[ 4] = 32'h00400000;
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phase_off[ 5] = 32'h00500000;
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phase_off[ 6] = 32'h00600000;
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phase_off[ 7] = 32'h00700000;
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phase_off[ 8] = 32'h00800000;
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phase_off[ 9] = 32'h00900000;
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phase_off[10] = 32'h00A00000;
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phase_off[11] = 32'h00B00000;
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phase_off[12] = 32'h00C00000;
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phase_off[13] = 32'h00D00000;
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phase_off[14] = 32'h00E00000;
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phase_off[15] = 32'h00F00000;
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end
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endtask
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign aresetn = ~areset;
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genvar i;
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generate
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for(i=0;i<16;i=i+1) begin : pack
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assign phase_inc_array[32*i+31 : 32*i] = phase_inc[i];
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assign phase_off_array[32*i+31 : 32*i] = phase_off[i];
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end
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endgenerate
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generate
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for(i=0;i<16;i=i+1) begin : unpack
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assign wave_data[i] = sine_wave_array[9*i+8 : 9*i];
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end
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endgenerate
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endmodule |