110 lines
2.2 KiB
Verilog
110 lines
2.2 KiB
Verilog
`timescale 1ns/1ps
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module rhs2116_mod#
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(
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parameter DATA_WIDTH = 32 ,
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parameter WIRE_DELAY = 11
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)
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(
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input cs ,
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input sclk ,
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input mosi ,
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output reg miso
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);
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg rst_n ;
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reg [32 - 1:0] serial_in ;
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reg [ 8 - 1:0] rx_cnt ;
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reg [32 - 1:0] rx_data ;
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reg [16 - 1:0] cnv_res_hg ;
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reg [ 8 - 1:0] tx_cnt ;
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reg [32 - 1:0] tx_data ;
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reg [32 - 1:0] tx_data_t ;
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//*****************************************************************************
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initial begin
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#100 rst_n = 0;
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#100 rst_n = 1;
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end
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//RX
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always @ ( posedge sclk or negedge rst_n or posedge cs ) begin
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if( !rst_n )
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rx_cnt <= 0;
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else if( cs )
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rx_cnt <= 0;
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else if ( rx_cnt != 8'hFF )
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rx_cnt <= rx_cnt + 1'b1;
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end
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always @ ( posedge sclk or negedge rst_n or negedge cs ) begin
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if( !rst_n )
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serial_in <= 0;
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else if( cs )
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serial_in <= 0;
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else
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serial_in <= {serial_in[30:0], mosi};
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end
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always @ ( rx_cnt ) begin
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if( rx_cnt == 32 )
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rx_data <= serial_in;
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end
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//data
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always @ ( negedge rst_n or posedge cs ) begin
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if( !rst_n ) begin
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cnv_res_hg <= 0;
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tx_data <= 0;
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end else if( rx_cnt == 32 ) begin
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case ( rx_data[31:30] )
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2'b00: begin
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tx_data <= {cnv_res_hg, 6'd0, cnv_res_hg[15:6]};
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cnv_res_hg <= cnv_res_hg + 1'b1;
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end
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2'b11:
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tx_data <= {16'h0000, 16'hFFFF};
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default:
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tx_data <= 32'hZZZZZZZZ;
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endcase
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end
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end
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always @ ( negedge rst_n or negedge cs ) begin
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if ( !rst_n )
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tx_data_t <= 0;
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else
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tx_data_t <= tx_data;
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end
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//TX
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always @ ( posedge sclk or negedge rst_n or posedge cs ) begin
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if( !rst_n )
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tx_cnt <= 8'd31;
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else if( cs )
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tx_cnt <= 8'd31;
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else if ( tx_cnt != 8'h0 )
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tx_cnt <= tx_cnt - 1'b1;
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end
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always @ ( negedge sclk or negedge rst_n or negedge cs ) begin
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if( !rst_n )
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miso <= 1'bX;
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else if( ~cs )
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#10 miso <= tx_data_t[tx_cnt];
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else
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#12 miso <= tx_data_t[tx_cnt];
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end
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endmodule
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