80 lines
1.7 KiB
Verilog
80 lines
1.7 KiB
Verilog
`timescale 1 ns / 1 ps
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module led_ctrl#
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(
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parameter CLK_PERIOD = 10
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)
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(
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input clk ,
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input rst_n ,
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input [3-1:0] cmd ,
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output reg led
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);
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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wire st_off ;
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wire st_on ;
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wire st_blink ;
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wire st_breath ;
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wire led_blink ;
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wire led_breath ;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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pwm_gen#
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(
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.DATA_WIDTH ( 28 )
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)
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u_pwm_gen_blink
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( st_blink ),
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.period ( 28'hBEBC200 ),
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.duty ( 28'h5F5E100 ),
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.pwm ( led_blink )
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);
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breath_gen#
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(
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.CLK_PERIOD ( CLK_PERIOD )
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)
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u_breath_gen
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.enable ( st_breath ),
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.pwm ( led_breath )
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);
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//*****************************************************************************
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always @ ( * ) begin
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if (st_off)
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led <= 1'b0;
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else if (st_on)
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led <= 1'b1;
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else if (st_blink)
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led <= led_blink;
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else if (st_breath)
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led <= led_breath;
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else
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led <= 1'b0;
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign st_off = (cmd == 3'b000)? 1'b1:1'b0;
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assign st_on = (cmd == 3'b001)? 1'b1:1'b0;
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assign st_blink = (cmd == 3'b010)? 1'b1:1'b0;
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assign st_breath= (cmd == 3'b011)? 1'b1:1'b0;
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endmodule
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