78 lines
2.2 KiB
Verilog
78 lines
2.2 KiB
Verilog
`timescale 1 ns / 1 ps
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module emg_top#
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(
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parameter CLK_PERIOD = 10 ,
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parameter SPI_CLK_DIV = 5 ,
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parameter CHIPSET_QTY = 1 ,
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parameter SPI_TRANS_PERIOD = 2000
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output interrupt ,
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//------------------------------------------ FIFO: emg output
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output [32-1:0] axis_txd_tdata ,
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output axis_txd_tlast ,
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input axis_txd_tready ,
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output axis_txd_tvalid ,
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//------------------------------------------ device interface
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output cs ,
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output sclk ,
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output mosi ,
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input miso ,
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input drdy ,
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output start ,
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output reset_n ,
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output pwdn_n
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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//*****************************************************************************
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// Procedural blocks
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//*****************************************************************************
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign bram_dout = 0;
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assign interrupt = 1'b0;
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assign axis_txd_tdata = 0;
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assign axis_txd_tlast = 1'b0;
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assign axis_txd_tvalid = 1'b0;
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assign cs = 1'b0;
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assign sclk = 1'b0;
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assign mosi = 1'b0;
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assign start = 1'b0;
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assign reset_n = 1'b1;
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assign pwdn_n = 1'b1;
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endmodule
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