286 lines
8.0 KiB
Verilog
286 lines
8.0 KiB
Verilog
`timescale 1ns/1ps
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module eeg_top_tb();
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//*****************************************************************************
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// Parameter definition
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//*****************************************************************************
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localparam T_CLK = 10; //ns
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localparam SPIS_QTY = 4;
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localparam CHIPSET_QTY = 8;
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localparam BRAM_ADDR_TEST_RO = 13'h0000;
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localparam BRAM_ADDR_TEST_RW = 13'h0004;
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localparam BRAM_ADDR_EEG_ER = 13'h0040;
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localparam BRAM_ADDR_EEG_CR = 13'h0044;
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localparam BRAM_ADDR_EEG_SR = 13'h0048;
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localparam BRAM_ADDR_EEG_TR = 13'h0100;
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localparam BRAM_ADDR_EEG_RR = 13'h0200;
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localparam BRAM_ADDR_EEG_TR_MASK = 13'h1F00;
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localparam BRAM_ADDR_EEG_RR_MASK = 13'h1F00;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg clk ;
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reg rst_n ;
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reg [13-1:0] bram_eeg_addr ;
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reg bram_eeg_clk ;
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reg [32-1:0] bram_eeg_din ;
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wire [32-1:0] bram_eeg_dout ;
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reg bram_eeg_en ;
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reg bram_eeg_rst ;
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reg [ 4-1:0] bram_eeg_we ;
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wire interrupt ;
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reg [32-1:0] trigger_tdata ;
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reg trigger_tvalid ;
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reg [32-1:0] read_data ;
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wire [32-1:0] axis_record_tdata ;
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wire axis_record_tlast ;
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reg axis_record_tready ;
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wire axis_record_tvalid ;
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wire [CHIPSET_QTY-1:0] cs_w ;
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wire [ SPIS_QTY-1:0] sclk_w ;
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wire [ SPIS_QTY-1:0] mosi_w ;
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wire [ SPIS_QTY-1:0] miso_w ;
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wire [ SPIS_QTY-1:0] drdy_w ;
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wire start_w ;
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wire [CHIPSET_QTY-1:0] cs ;
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wire [CHIPSET_QTY-1:0] sclk ;
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wire [CHIPSET_QTY-1:0] mosi ;
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wire [CHIPSET_QTY-1:0] miso ;
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wire [CHIPSET_QTY-1:0] drdy ;
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wire [CHIPSET_QTY-1:0] start ;
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integer n;
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genvar i;
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//*****************************************************************************
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// Instantiation
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//*****************************************************************************
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eeg_top#
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(
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.CLK_PERIOD ( T_CLK )
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)
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DUT
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.bram_addr ( bram_eeg_addr ),
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.bram_clk ( bram_eeg_clk ),
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.bram_din ( bram_eeg_din ),
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.bram_dout ( bram_eeg_dout ),
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.bram_en ( bram_eeg_en ),
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.bram_rst ( bram_eeg_rst ),
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.bram_we ( bram_eeg_we ),
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.interrupt ( interrupt ),
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.trigger_tdata ( trigger_tdata ),
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.trigger_tvalid ( trigger_tvalid ),
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//------------------------------------------ FIFO: eeg output
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.axis_record_tdata ( axis_record_tdata ),
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.axis_record_tlast ( axis_record_tlast ),
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.axis_record_tready ( axis_record_tready ),
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.axis_record_tvalid ( axis_record_tvalid ),
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//------------------------------------------ device spi
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.cs ( cs_w ),
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.sclk ( sclk_w ),
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.mosi ( mosi_w ),
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.miso ( miso_w ),
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.drdy ( drdy_w ),
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.start ( start_w )
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);
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generate
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for(i=0; i<CHIPSET_QTY; i=i+1) begin : spi
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ads1299_mod u_ads1299_mod
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(
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.cs ( cs[i] ),
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.sclk ( sclk[i] ),
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.mosi ( mosi[i] ),
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.miso ( miso[i] ),
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.drdy ( drdy[i] ),
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.start ( start[i] )
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);
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end
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endgenerate
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//*****************************************************************************
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always #( T_CLK/2.0 ) clk = !clk;
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initial begin
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Initial();
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#100 rst_n = 0;
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#100 rst_n = 1;
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#100
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/*
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//SDATAC
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00000011);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00000011);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00000011);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000011);
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100});
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
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#4_000
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101});
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
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#4_000
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//READ ID
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b1100, 4'b1100, 4'b1100, 4'b1100});
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
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#10_000
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read_bram_eeg(BRAM_ADDR_EEG_RR+4'h0, read_data);
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#100
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// $stop;
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b1101, 4'b1101, 4'b1101, 4'b1101});
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
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#10_000
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//
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#7_000
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100});
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
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#3_000
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
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write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101});
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
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*/
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#3_000
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@ ( posedge clk );
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write_bram_eeg(BRAM_ADDR_EEG_CR, {1'b1, 15'd10, 16'd0});
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// #40_000
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// @ ( posedge clk );
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// $stop;
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end
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//*****************************************************************************
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// Task
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//*****************************************************************************
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task Initial;
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begin
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clk <= 1'b0 ;
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rst_n <= 1'b0 ;
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bram_eeg_addr <= 0 ;
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bram_eeg_clk <= 1'b0 ;
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bram_eeg_din <= 0 ;
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bram_eeg_en <= 1'b0 ;
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bram_eeg_rst <= 1'b0 ;
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bram_eeg_we <= 0 ;
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trigger_tdata <= 0 ;
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trigger_tvalid <= 1'b0 ;
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axis_record_tready <= 1'b1;
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end
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endtask
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task read_bram_eeg;
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input [12:0] addr;
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output [31:0] data;
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begin
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@ ( posedge clk );
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bram_eeg_addr <= addr;
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bram_eeg_en <= 1;
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bram_eeg_we <= 4'h0;
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@ ( posedge clk );
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bram_eeg_en <= 0;
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@ ( posedge clk );
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data <= bram_eeg_dout;
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end
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endtask
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task write_bram_eeg;
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input [12:0] addr;
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input [31:0] data;
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begin
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@ ( posedge clk );
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bram_eeg_addr <= addr;
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bram_eeg_din <= data;
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bram_eeg_en <= 1;
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bram_eeg_we <= 4'hF;
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@ ( posedge clk );
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bram_eeg_en <= 0;
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bram_eeg_we <= 4'h0;
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end
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endtask
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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generate
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for(i=0;i<CHIPSET_QTY;i=i+1) begin : mapping_spi
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assign cs[i] = cs_w[i];
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assign sclk[i] = sclk_w[i/2];
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assign mosi[i] = mosi_w[i/2];
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assign start[i] = start_w;
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end
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endgenerate
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generate
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for(i=0;i<SPIS_QTY;i=i+1) begin : mapping_reg
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assign drdy_w[i] = drdy[2*i];
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end
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endgenerate
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assign miso_w[0] = (~cs_w[0])? miso[0]:((~cs_w[1])? miso[1]:1'bZ);
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assign miso_w[1] = (~cs_w[2])? miso[2]:((~cs_w[3])? miso[3]:1'bZ);
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assign miso_w[2] = (~cs_w[4])? miso[4]:((~cs_w[5])? miso[5]:1'bZ);
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assign miso_w[3] = (~cs_w[6])? miso[6]:((~cs_w[7])? miso[7]:1'bZ);
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endmodule |