263 lines
6.1 KiB
Verilog
263 lines
6.1 KiB
Verilog
`timescale 1 ns / 1 ps
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module ads1299_spi#
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(
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parameter CLK_PERIOD = 10 ,
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parameter CLK_DIV = 3 , // max: 255
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parameter DATA_WIDTH = 8 , // max: 255
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parameter NO_OF_SLAVES = 1
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)
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(
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input clk ,
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input rst_n ,
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input [ 8-1:0] t_cs_n ,
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input [ DATA_WIDTH-1:0] t_tdata ,
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input t_tlast ,
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output reg t_tready ,
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input t_tvalid ,
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output reg [ DATA_WIDTH-1:0] r_tdata ,
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output reg r_tlast ,
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output reg r_tvalid ,
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output [NO_OF_SLAVES-1:0] cs ,
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output sclk ,
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output mosi ,
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input miso
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam CNT_POS = CLK_DIV-1 ;
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localparam CNT_NEG = CLK_DIV*2-1 ;
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localparam T_SCCS = 2000/CLK_PERIOD ;
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localparam T_SCH = 600/CLK_PERIOD ;
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localparam IDLE = 4'd0;
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localparam TRANS_ST = 4'd1;
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localparam SCCS_ST = 4'd2;
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localparam CSH_ST = 4'd3;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [ 4-1:0] cstate ;
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reg [ 4-1:0] nstate ;
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reg [DATA_WIDTH-1:0] tx_data ;
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reg [DATA_WIDTH-1:0] rx_data ;
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reg clk_en ;
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reg [ 9-1:0] cnt ;
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reg sck_pos ;
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reg sck_neg ;
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reg [ 8-1:0] trans_cnt ;
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reg [ 8-1:0] slv_n ;
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reg [NO_OF_SLAVES-1:0] cs_r ;
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reg sclk_r ;
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reg [NO_OF_SLAVES-1:0] cs_release ;
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reg [ 8-1:0] t_sccs_cnt ;
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reg [ 8-1:0] t_sch_cnt ;
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reg read_flag ;
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//*****************************************************************************
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always@( posedge clk or negedge rst_n ) begin
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if( !rst_n ) cstate <= IDLE;
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else cstate <= nstate;
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end
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always@( * ) begin
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case ( cstate )
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IDLE:
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if ( t_tvalid )
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nstate <= TRANS_ST;
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else
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nstate <= IDLE;
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TRANS_ST:
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if( (trans_cnt == 0) && sck_neg )
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nstate <= (cs_release[slv_n])? SCCS_ST : IDLE;
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else
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nstate <= TRANS_ST;
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SCCS_ST:
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if ( t_sccs_cnt == T_SCCS - 1 )
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nstate <= CSH_ST;
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else
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nstate <= SCCS_ST;
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CSH_ST:
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if ( t_sch_cnt == T_SCH - 1 )
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nstate <= IDLE;
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else
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nstate <= CSH_ST;
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default:
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nstate <= IDLE;
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endcase
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n )
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t_tready <= 1'b0;
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else if ( nstate == IDLE )
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t_tready <= 1'b1;
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else if ( cstate == IDLE && nstate == IDLE )
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t_tready <= 1'b1;
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else
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t_tready <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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slv_n <= 0;
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end else if ( cstate == IDLE || nstate == IDLE ) begin
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slv_n <= t_cs_n;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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cs_release <= 1'b0;
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else if ( t_tvalid && t_tready && t_tlast )
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cs_release[slv_n] <= 1'b1;
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else if ( t_tvalid && t_tready )
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cs_release[slv_n] <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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cs_r <= {NO_OF_SLAVES{1'b1}};
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else if ( cstate == TRANS_ST )
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cs_r[slv_n] <= 1'b0;
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else if ( nstate == CSH_ST )
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cs_r[slv_n] <= cs_release[slv_n];
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if ( !rst_n ) begin
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tx_data <= 0;
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end else if ( t_tready && t_tvalid ) begin
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tx_data <= t_tdata;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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clk_en <= 0;
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else if ( ((cstate == IDLE) && (nstate == TRANS_ST)) || ((cstate == TRANS_ST) && (nstate != SCCS_ST)) )
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clk_en <= 1'b1;
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else if ( nstate == SCCS_ST || nstate == IDLE )
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clk_en <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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cnt <= 0;
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else if ( !clk_en )
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cnt <= 0;
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else if ( cnt == CLK_DIV*2-1 )
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cnt <= 0;
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else
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cnt <= cnt + 1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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sck_pos <= 0;
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else if ( clk_en && (cnt == CNT_POS) )
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sck_pos <= 1;
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else
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sck_pos <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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sck_neg <= 0;
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else if ( clk_en && (cnt == CNT_NEG) )
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sck_neg <= 1;
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else
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sck_neg <= 0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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sclk_r <= 0;
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else if ( sck_pos && nstate == TRANS_ST )
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sclk_r <= 1'b1;
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else if ( sck_neg )
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sclk_r <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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trans_cnt <= DATA_WIDTH;
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else if ( cstate == IDLE )
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trans_cnt <= DATA_WIDTH;
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else if ( sck_pos && (trans_cnt != 0) )
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trans_cnt <= trans_cnt - 1'b1;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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rx_data <= 0;
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else if ( sck_neg )
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rx_data[trans_cnt] <= miso;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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read_flag <= 1'b0;
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else if ( cstate == TRANS_ST && nstate != TRANS_ST )
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read_flag <= 1'b1;
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else
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read_flag <= 1'b0;
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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r_tvalid <= 1'b0;
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r_tdata <= 0;
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r_tlast <= 1'b0;
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end else if ( read_flag ) begin
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r_tvalid <= 1'b1;
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r_tdata <= rx_data;
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r_tlast <= cs_release[slv_n];
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end else begin
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r_tvalid <= 1'b0;
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r_tlast <= 1'b0;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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t_sccs_cnt <= 0;
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end else if ( cstate != SCCS_ST ) begin
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t_sccs_cnt <= 0;
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end else begin
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t_sccs_cnt <= t_sccs_cnt + 1'b1;
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end
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end
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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t_sch_cnt <= 0;
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end else if ( cstate != CSH_ST ) begin
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t_sch_cnt <= 0;
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end else begin
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t_sch_cnt <= t_sch_cnt + 1'b1;
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end
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end
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//*****************************************************************************
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// Wire assignment
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//*****************************************************************************
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assign cs = cs_r;
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assign sclk = sclk_r;
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assign mosi = (trans_cnt==DATA_WIDTH)? 1'b0:tx_data[trans_cnt];
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endmodule
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