465 lines
20 KiB
Verilog
465 lines
20 KiB
Verilog
`timescale 1 ns / 1 ps
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module dac80508_controller (
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input wire clk, // 100MHz时钟
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input wire rst_n, // 复位信号（低有效）
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(*mark_debug="true"*)input wire stim_en,
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(*mark_debug="true"*)input wire imp_test_en ,
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(*mark_debug="true"*)input wire [23:0] stim_data ,
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(*mark_debug="true"*)input wire stim_data_en ,
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(*mark_debug="true"*)output reg cs_n, // 片选信号
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(*mark_debug="true"*)output reg sclk, // 串行时钟（分频后）
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(*mark_debug="true"*)output reg sdi, // 数据输出
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(*mark_debug="true"*)output reg [3:0] state ,
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//input wire [8*16-1:0] data_in, //数据输入
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(*mark_debug="true"*)input wire [23:0] data_in ,
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(*mark_debug="true"*)input wire imp_fifo_rd_en
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// input wire imp_data_en ,
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// (*mark_debug="true"*)input wire phase_en
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);
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parameter IDLE = 'b0001;
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parameter BROARDCAST_SET = 'b0010;
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parameter DAC80508_MID_INITIAL = 'b0011;
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parameter GAIN_SET_SINE = 'b0100;
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parameter WAIT_SEND_DATA = 'b0101;
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parameter WAIT_SEND_DATACS = 'b0110;
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parameter SEND_DATA = 'b0111;
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parameter SEND_DATA_CS = 'b1000;
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parameter SEND_DATA_CS1 = 'b1001;
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parameter DELAY = 'b1010;
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// (*mark_debug="true"*)reg [3:0] state;
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//reg [15:0] shift_reg ;
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//reg [4:0] bit_cnt ;
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// (*mark_debug="true"*)wire [2:0] channel ;
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// reg [6:0] cnt_1us ;
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// reg phase_en_dly ;
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(*mark_debug="true"*)reg [23:0] asyc_set ;
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(*mark_debug="true"*)reg [4:0] cmd_bit_count ;
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// (*mark_debug="true"*)reg start ;
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// (*mark_debug="true"*)reg start_dly ;
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// (*mark_debug="true"*)wire [15:0] data_in_o[0:7] ;
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// (*mark_debug="true"*)wire [23:0] data_in_c[0:7] ;
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(*mark_debug="true"*)reg [7:0] stim_wait_cnt ;
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(*mark_debug="true"*)reg [7:0] delay_wait_cnt ;
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(*mark_debug="true"*)wire [23:0] stim_data_dout ;
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(*mark_debug="true"*)wire fifo_empty ;
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(*mark_debug="true"*)reg fifo_rd_en ;
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// (*mark_debug="true"*)reg [15:0] imp_data_cnt ;
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// (*mark_debug="true"*)reg imp_data_pls ;
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// (*mark_debug="true"*)reg [2:0] channel_tmp ;
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// (*mark_debug="true"*)reg imp_data_start;
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(*mark_debug="true"*)wire [23:0] dac0_mid ;
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wire [23:0] dac1_mid ;
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wire [23:0] dac2_mid ;
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wire [23:0] dac3_mid ;
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wire [23:0] dac4_mid ;
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wire [23:0] dac5_mid ;
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wire [23:0] dac6_mid ;
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wire [23:0] dac7_mid ;
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(*mark_debug="true"*)reg [9:0] dac_mid_cnt ;
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wire [23:0] gain_set ;
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reg [5:0] gain_set_cnt ;
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//assign data_in_c[23:0][0:7]={4'b0,1'b1,channel[2:0],data_in_o[channel]};
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assign dac0_mid[23:0]=24'h88000;
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assign dac1_mid[23:0]=24'h98000;
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assign dac2_mid[23:0]=24'ha8000;
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assign dac3_mid[23:0]=24'hb8000;
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assign dac4_mid[23:0]=24'hc8000;
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assign dac5_mid[23:0]=24'hd8000;
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assign dac6_mid[23:0]=24'he8000;
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assign dac7_mid[23:0]=24'hf8000;
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assign gain_set[23:0]=24'h401ff ;
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// assign channel[2:0] = channel_tmp[2:0]-1 ;
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// genvar i;
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// generate
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// for(i=0;i<8;i=i+1) begin : unpack //正弦波分配
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// assign data_in_o[i] = data_in[16*i+15 : 16*i];
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// end
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// endgenerate
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// genvar j;
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// generate
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// for(j=0;j<8;j=j+1) begin : unpack1 //正弦波前面加上控制
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// assign data_in_c[j] = {4'b0,1'b1,channel[2:0],data_in_o[j]};
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// end
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// endgenerate
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// always @(posedge clk or negedge rst_n) begin //阻抗测试加上phase_en
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// if (!rst_n) begin
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// phase_en_dly <= 1'b0;
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// end else begin
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// phase_en_dly <= phase_en ;
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// end
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// end
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// always @(posedge clk or negedge rst_n) begin //阻抗测试开始
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// if (!rst_n) begin
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// start <= 1'b0;
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// end else if(imp_test_en==1'b1)begin
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// if((phase_en==1'b1)&&(phase_en_dly==1'b0))begin
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// start <= 1'b1;
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// end
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// else begin
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// start <= start ;
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// end
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// end else begin
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// start <= 1'b0;
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// end
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// end
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// always @(posedge clk or negedge rst_n) begin //阻抗测试开始打拍
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// if (!rst_n) begin
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// start_dly <= 1'b0;
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// end else begin
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// start_dly <= start;
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// end
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// end
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// always @(posedge clk or negedge rst_n) begin //阻抗测试计时
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// if (!rst_n) begin
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// cnt_1us[6:0] <= 7'b0;
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// end else if(start==1'b1)begin //start==1'b1
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// if(cnt_1us[6:0]==7'd99)
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// cnt_1us[6:0] <= 7'b0;
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// else
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// cnt_1us[6:0] <= cnt_1us[6:0]+1'b1;
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// end else begin
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// cnt_1us[6:0] <= 7'b0 ;
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// end
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// end
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// always @(posedge clk or negedge rst_n) begin //阻抗测试通道对齐
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// if (!rst_n) begin
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// imp_data_start <= 1'b0;
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// end else if(imp_test_en)begin
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// if(imp_data_en==1'b1)begin
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// imp_data_start <= 1'b1;
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// end else begin
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// imp_data_start <= imp_data_start;
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// end
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// end else begin
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// imp_data_start <= 1'b0;
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// end
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// end
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// always @(posedge clk or negedge rst_n) begin //阻抗测试通道对齐
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// if (!rst_n) begin
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// imp_data_cnt[15:0] <= 16'b0;
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// end else if(imp_data_start==1'b1)begin
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// if(imp_data_en==1'b1)begin
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// imp_data_cnt[15:0] <= 16'b0;
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// end else if(imp_data_cnt[15:0]==16'd3000)begin
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// imp_data_cnt[15:0] <= imp_data_cnt[15:0] ;
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// end else begin
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// imp_data_cnt[15:0] <= imp_data_cnt[15:0] + 1'b1 ;
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// end
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// end else begin
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// imp_data_cnt[15:0] <= 16'b0;
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// end
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// end
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// always @(posedge clk or negedge rst_n) begin //阻抗测试通道对齐
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// if (!rst_n) begin
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// imp_data_pls <= 1'b0;
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// channel_tmp[2:0] <= 3'b0;
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// end else if(imp_test_en==1'b1)begin
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// if((imp_data_cnt[15:0]==16'd1)||(imp_data_cnt[15:0]==16'd301)||(imp_data_cnt[15:0]==16'd601)||(imp_data_cnt[15:0]==16'd901)||(imp_data_cnt[15:0]==16'd1201)||(imp_data_cnt[15:0]==16'd1501)||(imp_data_cnt[15:0]==16'd1801)||(imp_data_cnt[15:0]==16'd2101))begin
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// imp_data_pls <= 1'b1;
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// channel_tmp[2:0] <= channel_tmp[2:0]+1'b1;
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// end else begin
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// imp_data_pls <= 1'b0;
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// channel_tmp[2:0] <= channel_tmp[2:0];
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// end
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// end else begin
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// imp_data_pls <= 1'b0;
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// channel_tmp[2:0] <= 3'b0;
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// end
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// end
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// always @(posedge clk or negedge rst_n) begin //刺激等待时间
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// if (!rst_n) begin
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// stim_wait_cnt[7:0] <= 8'b0;
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// end else if(imp_test_en==1'b1)begin
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// stim_wait_cnt[7:0] <= 8'b0;
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// end else begin
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// if(stim_data_en==1'b1)//stim_en==1'b1
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// stim_wait_cnt[7:0] <= 8'b0;
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// else if(stim_wait_cnt[7:0]==8'd199)
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// stim_wait_cnt[7:0] <= stim_wait_cnt[7:0] ;
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// else
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// stim_wait_cnt[7:0] <= stim_wait_cnt[7:0]+1'b1 ;
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// end
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// end
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always @(posedge clk or negedge rst_n) begin //刺激等待时间
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if (!rst_n) begin
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stim_wait_cnt[7:0] <= 8'b0;
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end else if((fifo_empty==1'b0)&&(state == WAIT_SEND_DATA))begin
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stim_wait_cnt[7:0] <= stim_wait_cnt[7:0]+1'b1;
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end else begin
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stim_wait_cnt[7:0] <= 8'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin //刺激等待时间
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if (!rst_n) begin
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stim_wait_cnt[7:0] <= 8'b0;
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end else if((fifo_empty==1'b0)&&(state == WAIT_SEND_DATA))begin
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stim_wait_cnt[7:0] <= stim_wait_cnt[7:0]+1'b1;
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end else begin
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stim_wait_cnt[7:0] <= 8'b0;
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end
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end
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always @(posedge clk or negedge rst_n) begin //刺激等待时间
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if (!rst_n) begin
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fifo_rd_en <= 1'b0;
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end else if(imp_test_en==1'b1)begin
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fifo_rd_en <= 1'b0;
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end else if((fifo_empty==1'b0)&&(state == WAIT_SEND_DATA)&&(stim_wait_cnt[7:0]==8'd3))begin
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fifo_rd_en <= 1'b1;
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end else begin
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fifo_rd_en <= 1'b0;
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end
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end
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// 主控制逻辑
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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state <= IDLE;
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sclk <= 0;
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cs_n <= 1;
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//bit_cnt <= 5'b0 ;
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//shift_reg[15:0] <= 16'b0;
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asyc_set[23:0] <= 24'h20000;//set broadcast
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sdi <= 0 ;
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cmd_bit_count[4:0] <= 5'd0;
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dac_mid_cnt[9:0] <= 10'b0 ;
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gain_set_cnt[5:0] <= 6'd0 ;
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delay_wait_cnt[7:0] <= 8'b0 ;
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end else begin
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case (state)
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IDLE: begin //进入IDLE模式
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cs_n <= 0;
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cmd_bit_count[4:0] <= 5'd23;
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state <= BROARDCAST_SET;
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delay_wait_cnt[7:0] <= 8'b0 ;
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end
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BROARDCAST_SET:begin //进入广播模式
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sclk <= ~sclk ;
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if(cmd_bit_count>0)begin
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sdi <= asyc_set[cmd_bit_count];
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if(sclk)cmd_bit_count<=cmd_bit_count-1 ;
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end else if(sclk) begin
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cs_n <= 0; //cs_n <= 1;
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sclk <= ~sclk;
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sdi <= asyc_set[0];
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state <= DAC80508_MID_INITIAL ;//WAIT_SEND_DATA ;
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end
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end
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DAC80508_MID_INITIAL:begin //初始值每个通道设置为1.25V
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if(dac_mid_cnt[9:0]==10'd1022)begin
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dac_mid_cnt[9:0] <= 10'd0 ;
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state <= GAIN_SET_SINE;
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end else begin
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dac_mid_cnt[9:0] <= dac_mid_cnt[9:0] + 1'b1 ;
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state <= state;
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end
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if((dac_mid_cnt[9:0]>=10'd1)&&(dac_mid_cnt[9:0]<=10'd52)||(dac_mid_cnt[9:0]>=10'd57)&&(dac_mid_cnt[9:0]<=10'd108)||(dac_mid_cnt[9:0]>=10'd113)&&(dac_mid_cnt[9:0]<=10'd164)||(dac_mid_cnt[9:0]>=10'd169)&&(dac_mid_cnt[9:0]<=10'd220)||
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(dac_mid_cnt[9:0]>=10'd225)&&(dac_mid_cnt[9:0]<=10'd276)||(dac_mid_cnt[9:0]>=10'd281)&&(dac_mid_cnt[9:0]<=10'd332)||(dac_mid_cnt[9:0]>=10'd337)&&(dac_mid_cnt[9:0]<=10'd388)||(dac_mid_cnt[9:0]>=10'd393)&&(dac_mid_cnt[9:0]<=10'd444))
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cs_n <= 0 ;
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else
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cs_n <= 1 ;
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if((dac_mid_cnt[9:0]>=10'd3)&&(dac_mid_cnt[9:0]<=10'd50)||(dac_mid_cnt[9:0]>=10'd59)&&(dac_mid_cnt[9:0]<=10'd106)||(dac_mid_cnt[9:0]>=10'd115)&&(dac_mid_cnt[9:0]<=10'd162)||(dac_mid_cnt[9:0]>=10'd171)&&(dac_mid_cnt[9:0]<=10'd218)||
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(dac_mid_cnt[9:0]>=10'd227)&&(dac_mid_cnt[9:0]<=10'd274)||(dac_mid_cnt[9:0]>=10'd283)&&(dac_mid_cnt[9:0]<=10'd330)||(dac_mid_cnt[9:0]>=10'd339)&&(dac_mid_cnt[9:0]<=10'd386)||(dac_mid_cnt[9:0]>=10'd395)&&(dac_mid_cnt[9:0]<=10'd442))
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sclk <= ~sclk ;
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else
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sclk <= 0 ;
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if((dac_mid_cnt[9:0]==10'd0)||(dac_mid_cnt[9:0]==10'd56)||(dac_mid_cnt[9:0]==10'd112)||(dac_mid_cnt[9:0]==10'd168)||(dac_mid_cnt[9:0]==10'd224)||(dac_mid_cnt[9:0]==10'd280)||(dac_mid_cnt[9:0]==10'd336)||(dac_mid_cnt[9:0]==10'd392))begin
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cmd_bit_count[4:0] <= 5'd23;
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sdi <= 1'b1 ;
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end else if(cmd_bit_count[4:0]>0)begin
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if(sclk)cmd_bit_count <= cmd_bit_count-1 ;
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if((dac_mid_cnt[9:0]>=10'd3)&&(dac_mid_cnt[9:0]<=10'd50))
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sdi <= dac0_mid[cmd_bit_count];
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else if((dac_mid_cnt[9:0]>=10'd59)&&(dac_mid_cnt[9:0]<=10'd106))
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sdi <= dac1_mid[cmd_bit_count];
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else if((dac_mid_cnt[9:0]>=10'd115)&&(dac_mid_cnt[9:0]<=10'd162))
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sdi <= dac2_mid[cmd_bit_count];
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else if((dac_mid_cnt[9:0]>=10'd171)&&(dac_mid_cnt[9:0]<=10'd218))
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sdi <= dac3_mid[cmd_bit_count];
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else if((dac_mid_cnt[9:0]>=10'd227)&&(dac_mid_cnt[9:0]<=10'd274))
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sdi <= dac4_mid[cmd_bit_count];
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else if((dac_mid_cnt[9:0]>=10'd283)&&(dac_mid_cnt[9:0]<=10'd330))
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sdi <= dac5_mid[cmd_bit_count];
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else if((dac_mid_cnt[9:0]>=10'd339)&&(dac_mid_cnt[9:0]<=10'd386))
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sdi <= dac6_mid[cmd_bit_count];
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else if((dac_mid_cnt[9:0]>=10'd395)&&(dac_mid_cnt[9:0]<=10'd442))
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sdi <= dac7_mid[cmd_bit_count];
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else
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sdi <= 1'b0 ;
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end else begin
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cmd_bit_count[4:0] <= cmd_bit_count[4:0] ;
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sdi <= 1'b0 ;//sdi <= 1'b1
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end
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end
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GAIN_SET_SINE:begin //增加GAIN，先除以2，再乘以2
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dac_mid_cnt[9:0] <= 10'b0 ;
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if(gain_set_cnt[5:0]==6'd55)begin
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gain_set_cnt[5:0] <= 6'd0 ;
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state <= WAIT_SEND_DATA;
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end else begin
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gain_set_cnt[5:0] <= gain_set_cnt[5:0] + 1'b1 ;
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state <= state;
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end
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if((gain_set_cnt[5:0]>=6'd1)&&(gain_set_cnt[5:0]<=6'd52))
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cs_n <= 0 ;
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else
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cs_n <= 1 ;
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if((gain_set_cnt[5:0]>=6'd3)&&(gain_set_cnt[5:0]<=6'd50))
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sclk <= ~sclk ;
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else
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sclk <= 0 ;
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if(gain_set_cnt[5:0]==6'd0)begin
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cmd_bit_count[4:0] <= 5'd23;
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sdi <= 1'b1 ;
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end else if(cmd_bit_count[4:0]>0)begin
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if(sclk)cmd_bit_count <= cmd_bit_count-1 ;
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if((gain_set_cnt[5:0]>=6'd3)&&(gain_set_cnt[5:0]<=6'd50))
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sdi <= gain_set[cmd_bit_count];
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else
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sdi <= 1'b0 ;
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end else begin
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cmd_bit_count[4:0] <= cmd_bit_count[4:0] ;
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sdi <= 1'b1 ;
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end
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end
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WAIT_SEND_DATA:begin //等待发送数据
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dac_mid_cnt[9:0] <= 10'b0 ;
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// if ((stim_en==1'b0)&&(imp_test_en==1'b0))begin
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// state <= DAC80508_MID_INITIAL ;
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// cs_n <= 1; // 使能片选
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// sdi <= 1'b0 ;//new add
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// delay_wait_cnt[7:0] <= 8'b0 ;
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if ( fifo_rd_en || imp_fifo_rd_en)begin //((start==1'b1)&&(start_dly==1'b0))imp_data_pls stim_data_en,stim_en imp_data_en
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state <= WAIT_SEND_DATACS;
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cs_n <= 1; // 使能片选
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sdi <= 1'b0 ;//new add
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delay_wait_cnt[7:0] <= 8'b0 ;
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//cmd_bit_count[4:0] <= 5'd23;
|
|
end
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|
end
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|
WAIT_SEND_DATACS:begin //等待CS_n
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|
dac_mid_cnt[9:0] <= 10'b0 ;
|
|
// if ((stim_en==1'b0)&&(imp_test_en==1'b0))begin
|
|
// state <= DAC80508_MID_INITIAL ;
|
|
// cs_n <= 1; // 使能片选
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|
// sdi <= 1'b0 ;//new add
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|
// delay_wait_cnt[7:0] <= 8'b0 ;
|
|
//end else begin
|
|
state <= SEND_DATA;
|
|
cs_n <= 0; // 使能片选
|
|
cmd_bit_count[4:0] <= 5'd23;
|
|
// end
|
|
end
|
|
SEND_DATA:begin //发送数据
|
|
dac_mid_cnt[9:0] <= 10'b0 ;
|
|
sclk <= ~sclk ;
|
|
// if ((stim_en==1'b0)&&(imp_test_en==1'b0))begin
|
|
// state <= DAC80508_MID_INITIAL ;
|
|
// cs_n <= 1; // 使能片选
|
|
// sdi <= 1'b0 ;//new add
|
|
// delay_wait_cnt[7:0] <= 8'b0 ;
|
|
if(cmd_bit_count>0)begin
|
|
cs_n <= 0;
|
|
sdi <= imp_test_en?data_in[cmd_bit_count]:stim_data_dout[cmd_bit_count];//data_in_c[channel][cmd_bit_count]:stim_data_dout[cmd_bit_count];
|
|
if(sclk)cmd_bit_count<=cmd_bit_count-1 ;
|
|
end else if((cmd_bit_count==0)&&(!sclk))begin //新增加，主要防止最后一个数据输出错误的问题
|
|
cs_n <= 0;
|
|
sdi <= imp_test_en?data_in[0]:stim_data_dout[0];//data_in_o[channel][0]:stim_data_dout[0];
|
|
//if(sclk)cmd_bit_count<=cmd_bit_count-1 ;
|
|
end else if(sclk) begin
|
|
cs_n <= 0;
|
|
sclk <= ~sclk;
|
|
//sdi <= imp_test_en?data_in_o[channel][0]:stim_data[0];//之前用这个有问题，正弦波输出有点毛刺
|
|
state <= SEND_DATA_CS ;
|
|
end
|
|
end
|
|
SEND_DATA_CS:begin //等待CS
|
|
// dac_mid_cnt[9:0] <= 10'b0 ;
|
|
// if ((stim_en==1'b0)&&(imp_test_en==1'b0))begin
|
|
// state <= DAC80508_MID_INITIAL ;
|
|
// cs_n <= 1; // 使能片选
|
|
// sdi <= 1'b0 ;//new add
|
|
// delay_wait_cnt[7:0] <= 8'b0 ;
|
|
//end else begin
|
|
cs_n <= 0;
|
|
state <= SEND_DATA_CS1 ;
|
|
sdi <= 0 ;
|
|
//end
|
|
end
|
|
SEND_DATA_CS1:begin //等待CS
|
|
// dac_mid_cnt[9:0] <= 10'b0 ;
|
|
// if ((stim_en==1'b0)&&(imp_test_en==1'b0))begin
|
|
// state <= DAC80508_MID_INITIAL ;
|
|
// cs_n <= 1; // 使能片选
|
|
// sdi <= 1'b0 ;//new add
|
|
// delay_wait_cnt[7:0] <= 8'b0 ;
|
|
// end else begin
|
|
cs_n <= 1;
|
|
state <= DELAY ;
|
|
// end
|
|
end
|
|
DELAY: begin //1us或2us等待时间
|
|
dac_mid_cnt[9:0] <= 10'b0 ;
|
|
delay_wait_cnt[7:0] <= delay_wait_cnt[7:0] + 1'b1 ;
|
|
// if ((stim_en==1'b0)&&(imp_test_en==1'b0))begin
|
|
// state <= DAC80508_MID_INITIAL ;
|
|
// cs_n <= 1; // 使能片选
|
|
// sdi <= 1'b0 ;//new add
|
|
if (imp_test_en==1'b1)begin
|
|
if(delay_wait_cnt[7:0]==8'd99)begin//cnt_1us[6:0]==7'd99
|
|
state <= WAIT_SEND_DATA;//WAIT_SEND_DATACS; // 1μs延时
|
|
end else begin
|
|
state <= state ;
|
|
end
|
|
end else if(delay_wait_cnt[7:0]==8'd199)begin // if(stim_wait_cnt[7:0]==8'd199)
|
|
state <= WAIT_SEND_DATA ;
|
|
end
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
fifo_generator_3 u_fifo_generator_3(
|
|
.full( ),
|
|
.din(stim_data[23:0]),
|
|
.wr_en(stim_data_en),
|
|
.empty(fifo_empty ),
|
|
.dout(stim_data_dout[23:0]),
|
|
.rd_en(fifo_rd_en),
|
|
.rst(~rst_n),
|
|
.wr_clk(clk),
|
|
.rd_clk(clk) //clk_100m
|
|
);
|
|
|
|
|
|
endmodule |