84 lines
2.2 KiB
Verilog
84 lines
2.2 KiB
Verilog
`timescale 1 ns / 1 ps
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module accel_config#
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(
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parameter CHANNLE_QTY = 64 ,
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parameter PRE_MSG_LEN = 24
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)
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(
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input clk ,
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input rst_n ,
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input [13-1:0] bram_addr ,
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input bram_clk ,
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input [32-1:0] bram_din ,
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output reg [32-1:0] bram_dout ,
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input bram_en ,
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input bram_rst ,
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input [ 4-1:0] bram_we ,
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output [32-1:0] t_tdata ,
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input t_tready ,
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output t_tvalid ,
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input [32-1:0] r_tdata ,
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input r_tvalid ,
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output stream_enable
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);
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//*****************************************************************************
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// localparam definition
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//*****************************************************************************
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localparam BRAM_ADDR_TEST_RO = 13'h0000;
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localparam BRAM_ADDR_TEST_RW = 13'h0004;
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//*****************************************************************************
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// Internal register and wire declarations
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//*****************************************************************************
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reg [32-1:0] test_data ;
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wire bram_wr_valid ;
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wire bram_rd_valid ;
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reg [ 8-1:0] pre_message[0:PRE_MSG_LEN-1] ;
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reg [ 8-1:0] ch_mapping2pc[0:CHANNLE_QTY-1] ;
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reg [ 8-1:0] upload_ch[0:CHANNLE_QTY/8-1] ;
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integer n;
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genvar i;
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//*****************************************************************************
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// Procedural blocks
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//*****************************************************************************
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//write bram/Set config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n )
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test_data <= 0;
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else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_TEST_RW ) )
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test_data <= bram_din;
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end
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//read bram/Get config
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always @ ( posedge clk or negedge rst_n ) begin
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if( !rst_n ) begin
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bram_dout <= 0;
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end else if ( bram_rd_valid ) begin
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if ( bram_addr == BRAM_ADDR_TEST_RO )
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bram_dout <= 32'h12345678;
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end
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end
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//*****************************************************************************
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// Continuous assignments
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//*****************************************************************************
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assign t_tdata = 0;
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assign t_tvalid = 1'b0;
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assign stream_enable = 1'b0;
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endmodule
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