128 lines
11 KiB
Plaintext
128 lines
11 KiB
Plaintext
Vivado Simulator v2023.1
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Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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Running: C:/Xilinx/Vivado/2023.1/bin/unwrapped/win64.o/xelab.exe --incr --debug typical --relax --mt 2 -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_14 -L processing_system7_vip_v1_0_16 -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L fifo_generator_v13_2_8 -L axi_lite_ipif_v3_0_4 -L lib_cdc_v1_0_2 -L interrupt_control_v3_1_4 -L axi_gpio_v2_0_30 -L dist_mem_gen_v8_0_13 -L lib_pkg_v1_0_2 -L lib_srl_fifo_v1_0_2 -L lib_fifo_v1_0_17 -L axi_quad_spi_v3_2_27 -L axi_datamover_v5_1_30 -L axi_sg_v4_1_16 -L axi_dma_v7_1_29 -L axi_bram_ctrl_v4_1_8 -L xlconstant_v1_1_7 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L axi_register_slice_v2_1_28 -L xlconcat_v2_1_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot pl_top_tb_behav xil_defaultlib.pl_top_tb xil_defaultlib.glbl -log elaborate.log
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Using 2 slave threads.
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Starting static elaboration
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Pass Through NonSizing Optimizer
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_sclk' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:422]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:423]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_spi_miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:424]
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WARNING: [VRFC 10-3091] actual bit length 4 differs from formal bit length 2 for port 'eeg_ads1299_drdy_n' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:425]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'eeg_ads1299_start' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:426]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_tr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 64 for port 'eeg_rr_array' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:124]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cnv' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'sck' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'mosi' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:514]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'miso' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:515]
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WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 4 for port 'debug_sig' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:521]
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WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 64 for port 'probe_in2' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:292]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:626]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:630]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:632]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:640]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:642]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_trigger_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:678]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:682]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_eeg16_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:684]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tlast' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:692]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 's_axis_emg_tvalid' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:694]
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WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 48 for port 'accel_data' [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top.v:696]
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WARNING: [VRFC 10-5021] port 'bram_cur_addr' is not connected on this instance [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:329]
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WARNING: [VRFC 10-3705] select index 4 into 'emg_ads1299_drdy_w' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1514]
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WARNING: [VRFC 10-3705] select index 4 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1520]
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WARNING: [VRFC 10-3705] select index 6 into 'eeg_ads1299_spi_cs' is out of bounds [D:/Project/spinal_stim/pl/spinal_stim_v4/c64_pro.srcs/sources_1/rtl/pl_top_tb.v:1521]
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Completed static elaboration
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Starting simulation data flow analysis
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Completed simulation data flow analysis
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Time Resolution for simulation is 1ps
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_cdc_sync_rst(INIT=0,INIT_SYN...
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Compiling module xpm.xpm_fifo_rst(CDC_DEST_SYNC_FF=3)
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Compiling module xpm.xpm_fifo_reg_bit
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=6...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=5...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=2...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=3...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=32,USE_...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w32_d32
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Compiling module xil_defaultlib.eeg_config(SPIS_QTY=2)
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Compiling module xil_defaultlib.ads1299_arrange_default
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Compiling module xil_defaultlib.ads1299_spi(NO_OF_SLAVES=2)
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Compiling module xil_defaultlib.ads1299_if
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=2)
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Compiling module xil_defaultlib.eeg_top_default
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Compiling module xil_defaultlib.ads1299_spi_default
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Compiling module xil_defaultlib.ads1299_if(SPI_SLAVE_QTY=1)
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Compiling module xil_defaultlib.eeg_upload(CHIPSET_QTY=1)
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Compiling module xil_defaultlib.eeg_top1(CHIPSET_QTY=1,SPIS_QTY=...
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Compiling module xil_defaultlib.cur_mon_config(CH_QTY=16)
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Compiling module xil_defaultlib.ad7689_dual_ctrl(CLK_PERIOD=500)
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Compiling module xil_defaultlib.ad7689_dual_if(CLK_PERIOD=500)
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Compiling module xil_defaultlib.acq_collect(CLK_PERIOD=500,SPI_Q...
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Compiling module xil_defaultlib.cur_ch_map(CLK_PERIOD=500,CH_QTY...
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Compiling module unisims_ver.GND
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Compiling module unisims_ver.FDRE_default
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Compiling module unisims_ver.CARRY4
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Compiling module unisims_ver.x_lut2_mux4
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Compiling module unisims_ver.LUT2
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Compiling module xil_defaultlib.c_add_s16_s32
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Compiling module xil_defaultlib.cur_monitor(CLK_PERIOD=500,CH_QT...
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Compiling module unisims_ver.LUT5
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Compiling module unisims_ver.LUT6
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Compiling module unisims_ver.LUT4
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Compiling module unisims_ver.x_lut1_mux2
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Compiling module unisims_ver.LUT1
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Compiling module unisims_ver.x_lut3_mux8
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Compiling module unisims_ver.LUT3
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Compiling module unisims_ver.MUXF8
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Compiling module unisims_ver.MUXF7
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Compiling module xil_defaultlib.vio_cur_flt_state
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_gray__2
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Compiling module unisims_ver.FDSE_default
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Compiling module unisims_ver.SRL16E_default
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Compiling module unisims_ver.RB36_INTERNAL_VLOG(READ_WIDTH_A=...
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Compiling module unisims_ver.RAMB36E1(READ_WIDTH_A=36,READ_WI...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_single_...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1_xpm_cdc_sync_rs...
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Compiling module xil_defaultlib.fifo_generator_1
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Compiling module xil_defaultlib.cur_mon_top(CLK_PERIOD=500)
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Compiling module xil_defaultlib.accel_top
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Compiling module xil_defaultlib.run_time_default
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Compiling module xil_defaultlib.upload_config(PRE_MSG_LEN=128)
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=8...
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Compiling module xpm.xpm_counter_updn(COUNTER_WIDTH=7...
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Compiling module xpm.xpm_memory_base(MEMORY_TYPE=1,ME...
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Compiling module xpm.xpm_fifo_base(FIFO_WRITE_DEPTH=1...
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Compiling module xpm.xpm_fifo_axis(FIFO_DEPTH=128,TDA...
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Compiling module axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(C_FAM...
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Compiling module xil_defaultlib.axis_data_fifo_w8_d128
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Compiling module xil_defaultlib.upload_sort_default
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Compiling module xil_defaultlib.upload_protocol_ql_default
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Compiling module xil_defaultlib.upload_protocol_intan
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Compiling module xil_defaultlib.upload_top
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_sync_stag...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_bhv_ver_a...
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Compiling module fifo_generator_v13_2_8.fifo_generator_v13_2_8_CONV_VER(...
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Compiling module fifo_generator_v13_2_8.fifo_generator_vlog_beh(C_DATA_C...
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Compiling module xil_defaultlib.fifo_generator_0
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Compiling module xil_defaultlib.eeg_emg_upload
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Compiling module xil_defaultlib.stim_config
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Compiling module xil_defaultlib.pl_top
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Compiling module xil_defaultlib.rhs2116_mod
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Compiling module xil_defaultlib.ads1299_mod
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Compiling module xil_defaultlib.pl_top_tb
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Compiling module xil_defaultlib.glbl
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Built simulation snapshot pl_top_tb_behav
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