222 lines
9.8 KiB
Plaintext
222 lines
9.8 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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| Date : Fri Sep 4 15:27:46 2026
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| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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| Command : report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb
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| Design : c64pro_top
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| Device : xc7z020clg400-2
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| Speed File : -2
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| Design State : Synthesized
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Memory
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3. DSP
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4. IO and GT Specific
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5. Clocking
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6. Specific Feature
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7. Primitives
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8. Black Boxes
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9. Instantiated Netlists
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1. Slice Logic
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--------------
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+-------------------------+-------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------------------+-------+-------+------------+-----------+-------+
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| Slice LUTs* | 7721 | 0 | 0 | 53200 | 14.51 |
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| LUT as Logic | 7721 | 0 | 0 | 53200 | 14.51 |
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| LUT as Memory | 0 | 0 | 0 | 17400 | 0.00 |
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| Slice Registers | 11803 | 0 | 0 | 106400 | 11.09 |
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| Register as Flip Flop | 11803 | 0 | 0 | 106400 | 11.09 |
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| Register as Latch | 0 | 0 | 0 | 106400 | 0.00 |
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| F7 Muxes | 1594 | 0 | 0 | 26600 | 5.99 |
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| F8 Muxes | 712 | 0 | 0 | 13300 | 5.35 |
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+-------------------------+-------+-------+------------+-----------+-------+
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* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
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Warning! LUT value is adjusted to account for LUT combining.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 49 | Yes | - | Set |
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| 11681 | Yes | - | Reset |
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| 64 | Yes | Set | - |
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| 9 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Memory
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---------
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+----------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------+------+-------+------------+-----------+-------+
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| Block RAM Tile | 0 | 0 | 0 | 140 | 0.00 |
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| RAMB36/FIFO* | 0 | 0 | 0 | 140 | 0.00 |
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| RAMB18 | 0 | 0 | 0 | 280 | 0.00 |
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+----------------+------+-------+------------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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3. DSP
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------
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+-----------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------+------+-------+------------+-----------+-------+
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| DSPs | 0 | 0 | 0 | 220 | 0.00 |
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+-----------+------+-------+------------+-----------+-------+
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4. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------------------------+------+-------+------------+-----------+-------+
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| Bonded IOB | 58 | 0 | 0 | 125 | 46.40 |
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| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
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| Bonded IOPADs | 0 | 0 | 0 | 130 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 0 | 4 | 0.00 |
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| PHASER_REF | 0 | 0 | 0 | 4 | 0.00 |
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| OUT_FIFO | 0 | 0 | 0 | 16 | 0.00 |
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| IN_FIFO | 0 | 0 | 0 | 16 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 0 | 4 | 0.00 |
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| IBUFDS | 0 | 0 | 0 | 121 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 16 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 16 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 200 | 0.00 |
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| ILOGIC | 0 | 0 | 0 | 125 | 0.00 |
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| OLOGIC | 0 | 0 | 0 | 125 | 0.00 |
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+-----------------------------+------+-------+------------+-----------+-------+
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5. Clocking
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-----------
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+------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+------------+------+-------+------------+-----------+-------+
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| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
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| BUFIO | 0 | 0 | 0 | 16 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 0 | 4 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 0 | 4 | 0.00 |
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| BUFMRCE | 0 | 0 | 0 | 8 | 0.00 |
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| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
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| BUFR | 0 | 0 | 0 | 16 | 0.00 |
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+------------+------+-------+------------+-----------+-------+
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6. Specific Feature
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-------------------
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+-------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------+------+-------+------------+-----------+-------+
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| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
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| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+------------+-----------+-------+
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7. Primitives
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-------------
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+----------+-------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+-------+---------------------+
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| FDCE | 11681 | Flop & Latch |
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| LUT6 | 4593 | LUT |
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| MUXF7 | 1594 | MuxFx |
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| LUT2 | 1186 | LUT |
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| LUT3 | 794 | LUT |
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| LUT5 | 783 | LUT |
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| MUXF8 | 712 | MuxFx |
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| LUT1 | 653 | LUT |
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| LUT4 | 541 | LUT |
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| CARRY4 | 436 | CarryLogic |
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| FDSE | 64 | Flop & Latch |
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| FDPE | 49 | Flop & Latch |
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| IBUF | 32 | IO |
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| OBUFT | 27 | IO |
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| OBUF | 26 | IO |
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| FDRE | 9 | Flop & Latch |
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+----------+-------+---------------------+
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8. Black Boxes
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--------------
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+------------------------------------+------+
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| Ref Name | Used |
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+------------------------------------+------+
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| c_add_s16_s32 | 3 |
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| axis_data_fifo_w8_d128 | 2 |
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| vio_cur_flt_state | 1 |
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| fifo_generator_1 | 1 |
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| fifo_generator_0 | 1 |
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| design_a9_1_smartconnect_0_0 | 1 |
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| design_a9_1_rst_ps7_0_50M_0 | 1 |
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| design_a9_1_processing_system7_0_0 | 1 |
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| design_a9_1_axis_data_fifo_2_0 | 1 |
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| design_a9_1_axis_data_fifo_1_1 | 1 |
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| design_a9_1_axis_data_fifo_1_0 | 1 |
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| design_a9_1_axis_data_fifo_0_0 | 1 |
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| design_a9_1_axi_smc_0 | 1 |
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| design_a9_1_axi_quad_spi_0_0 | 1 |
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| design_a9_1_axi_gpio_1_0 | 1 |
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| design_a9_1_axi_gpio_0_0 | 1 |
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| design_a9_1_axi_dma_2_0 | 1 |
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| design_a9_1_axi_dma_1_1 | 1 |
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| design_a9_1_axi_dma_1_0 | 1 |
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| design_a9_1_axi_dma_0_0 | 1 |
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| design_a9_1_axi_bram_ctrl_6_0 | 1 |
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| design_a9_1_axi_bram_ctrl_5_0 | 1 |
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| design_a9_1_axi_bram_ctrl_4_0 | 1 |
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| design_a9_1_axi_bram_ctrl_3_1 | 1 |
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| design_a9_1_axi_bram_ctrl_3_0 | 1 |
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| design_a9_1_axi_bram_ctrl_2_0 | 1 |
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| design_a9_1_axi_bram_ctrl_1_0 | 1 |
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| design_a9_1_axi_bram_ctrl_0_0 | 1 |
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| design_a9_1_Z_IO_0 | 1 |
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| design_a9_1_ZCHECK_SPI_0 | 1 |
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| design_a9_1_STIM_SPI_0 | 1 |
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| design_a9_1_CHANN_SEL_0 | 1 |
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| design_a9_1_CHANN_EN_2 | 1 |
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| design_a9_1_CHANN_EN_1 | 1 |
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| design_a9_1_CHANN_EN_0 | 1 |
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+------------------------------------+------+
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9. Instantiated Netlists
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------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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