1402 lines
214 KiB
Plaintext
1402 lines
214 KiB
Plaintext
#-----------------------------------------------------------
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# Vivado v2023.1 (64-bit)
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# SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
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# IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
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# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
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# Start of session at: Fri Sep 4 15:23:24 2026
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# Process ID: 8436
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# Current directory: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1
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# Command line: vivado.exe -log c64pro_top.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source c64pro_top.tcl
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# Log file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/c64pro_top.vds
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# Journal file: D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1\vivado.jou
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# Running On: DESKTOP-VN054CM, OS: Windows, CPU Frequency: 3696 MHz, CPU Physical cores: 10, Host memory: 171579 MB
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#-----------------------------------------------------------
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source c64pro_top.tcl -notrace
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create_project: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1467.680 ; gain = 160.094
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INFO: [IP_Flow 19-234] Refreshing IP repositories
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INFO: [IP_Flow 19-1704] No user IP repositories specified
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INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2023.1/data/ip'.
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add_files: Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1607.059 ; gain = 139.379
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Command: synth_design -top c64pro_top -part xc7z020clg400-2
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Starting synth_design
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Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
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INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
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INFO: [Device 21-403] Loading part xc7z020clg400-2
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INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
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INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
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INFO: [Synth 8-7075] Helper process launched with PID 36164
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INFO: [Synth 8-11241] undeclared symbol 'cur_int', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:510]
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INFO: [Synth 8-11241] undeclared symbol 'debug_sig_cur', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:521]
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INFO: [Synth 8-11241] undeclared symbol 'accel_spi_cs', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:545]
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INFO: [Synth 8-11241] undeclared symbol 'accel_spi_sclk', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:546]
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INFO: [Synth 8-11241] undeclared symbol 'accel_spi_mosi', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:547]
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INFO: [Synth 8-11241] undeclared symbol 'accel_spi_miso', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:548]
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INFO: [Synth 8-11241] undeclared symbol 'accel_int0', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:549]
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INFO: [Synth 8-11241] undeclared symbol 'accel_int1', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:550]
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INFO: [Synth 8-11241] undeclared symbol 'emg_ads1299_pwdn_n', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:612]
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INFO: [Synth 8-11241] undeclared symbol 'led_wifi', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:673]
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INFO: [Synth 8-11241] undeclared symbol 'clear_int', assumed default net type 'wire' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:153]
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---------------------------------------------------------------------------------
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Starting RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 2465.742 ; gain = 410.441
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---------------------------------------------------------------------------------
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INFO: [Synth 8-6157] synthesizing module 'c64pro_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_wrapper' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v:13]
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INFO: [Synth 8-6157] synthesizing module 'IOBUF' [C:/Xilinx/Vivado/2023.1/scripts/rt/data/unisim_comp.v:76334]
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INFO: [Synth 8-6155] done synthesizing module 'IOBUF' (0#1) [C:/Xilinx/Vivado/2023.1/scripts/rt/data/unisim_comp.v:76334]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:13]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_gpio_1_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_gpio_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_gpio_1_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_gpio_1_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_CHANN_EN_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_EN_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_CHANN_EN_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_EN_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_STIM_SPI_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_STIM_SPI_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_STIM_SPI_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_STIM_SPI_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'ip2intc_irpt' of module 'design_a9_1_STIM_SPI_0' is unconnected for instance 'CUR_SPI' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1231]
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WARNING: [Synth 8-7023] instance 'CUR_SPI' of module 'design_a9_1_STIM_SPI_0' has 33 connections declared, but only 32 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1231]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_CHANN_EN_2' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_EN_2_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_CHANN_EN_2' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_EN_2_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_Z_IO_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_Z_IO_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_Z_IO_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_Z_IO_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'ip2intc_irpt' of module 'design_a9_1_Z_IO_0' is unconnected for instance 'GPIO' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1287]
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WARNING: [Synth 8-7023] instance 'GPIO' of module 'design_a9_1_Z_IO_0' has 23 connections declared, but only 22 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1287]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_CHANN_SEL_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_SEL_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_CHANN_SEL_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_SEL_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_ZCHECK_SPI_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_ZCHECK_SPI_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_ZCHECK_SPI_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_ZCHECK_SPI_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'ip2intc_irpt' of module 'design_a9_1_ZCHECK_SPI_0' is unconnected for instance 'STIM_SPI' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1333]
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WARNING: [Synth 8-7023] instance 'STIM_SPI' of module 'design_a9_1_ZCHECK_SPI_0' has 33 connections declared, but only 32 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1333]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_quad_spi_0_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_quad_spi_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_quad_spi_0_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_quad_spi_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'ip2intc_irpt' of module 'design_a9_1_axi_quad_spi_0_0' is unconnected for instance 'ZCHECK_SPI' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1366]
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WARNING: [Synth 8-7023] instance 'ZCHECK_SPI' of module 'design_a9_1_axi_quad_spi_0_0' has 33 connections declared, but only 32 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1366]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_CHANN_EN_1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_EN_1_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_CHANN_EN_1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_CHANN_EN_1_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_0_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_0_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_1_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_1_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_1_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_2_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_2_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_2_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_2_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_3_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_3_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_3_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_3_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_4_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_4_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_4_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_4_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_3_1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_3_1_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_3_1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_3_1_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_5_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_5_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_5_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_5_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_bram_ctrl_6_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_6_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_bram_ctrl_6_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_bram_ctrl_6_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_dma_0_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_dma_0_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'mm2s_prmry_reset_out_n' of module 'design_a9_1_axi_dma_0_0' is unconnected for instance 'axi_dma_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1655]
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WARNING: [Synth 8-7071] port 'm_axis_mm2s_tkeep' of module 'design_a9_1_axi_dma_0_0' is unconnected for instance 'axi_dma_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1655]
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WARNING: [Synth 8-7071] port 'axi_dma_tstvec' of module 'design_a9_1_axi_dma_0_0' is unconnected for instance 'axi_dma_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1655]
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WARNING: [Synth 8-7023] instance 'axi_dma_0' of module 'design_a9_1_axi_dma_0_0' has 40 connections declared, but only 37 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1655]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_dma_1_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_dma_1_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_1_0_stub.v:6]
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WARNING: [Synth 8-7071] port 's2mm_prmry_reset_out_n' of module 'design_a9_1_axi_dma_1_0' is unconnected for instance 'axi_dma_1' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1693]
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WARNING: [Synth 8-7071] port 'axi_dma_tstvec' of module 'design_a9_1_axi_dma_1_0' is unconnected for instance 'axi_dma_1' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1693]
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WARNING: [Synth 8-7023] instance 'axi_dma_1' of module 'design_a9_1_axi_dma_1_0' has 43 connections declared, but only 41 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1693]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_dma_1_1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_1_1_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_dma_1_1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_1_1_stub.v:6]
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WARNING: [Synth 8-7071] port 's2mm_prmry_reset_out_n' of module 'design_a9_1_axi_dma_1_1' is unconnected for instance 'axi_dma_2' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1735]
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WARNING: [Synth 8-7071] port 'axi_dma_tstvec' of module 'design_a9_1_axi_dma_1_1' is unconnected for instance 'axi_dma_2' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1735]
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WARNING: [Synth 8-7023] instance 'axi_dma_2' of module 'design_a9_1_axi_dma_1_1' has 43 connections declared, but only 41 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1735]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_dma_2_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_2_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_dma_2_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_dma_2_0_stub.v:6]
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WARNING: [Synth 8-7071] port 's2mm_prmry_reset_out_n' of module 'design_a9_1_axi_dma_2_0' is unconnected for instance 'axi_dma_3' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1777]
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WARNING: [Synth 8-7071] port 'axi_dma_tstvec' of module 'design_a9_1_axi_dma_2_0' is unconnected for instance 'axi_dma_3' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1777]
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WARNING: [Synth 8-7023] instance 'axi_dma_3' of module 'design_a9_1_axi_dma_2_0' has 43 connections declared, but only 41 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1777]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_gpio_0_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_gpio_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_gpio_0_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_gpio_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axi_smc_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_smc_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axi_smc_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axi_smc_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'M01_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M01_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M04_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M04_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M06_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M06_AXI_wstrb' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M06_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M07_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M07_AXI_wstrb' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M07_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M08_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M08_AXI_wstrb' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M08_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M10_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M10_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M11_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M11_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M12_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M12_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M13_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M13_AXI_wstrb' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M13_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M14_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M14_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M15_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M15_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M16_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M16_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M19_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M19_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M21_AXI_awprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7071] port 'M21_AXI_arprot' of module 'design_a9_1_axi_smc_0' is unconnected for instance 'axi_smc' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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WARNING: [Synth 8-7023] instance 'axi_smc' of module 'design_a9_1_axi_smc_0' has 458 connections declared, but only 426 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:1842]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axis_data_fifo_0_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axis_data_fifo_0_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axis_data_fifo_1_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_1_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axis_data_fifo_1_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_1_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axis_data_fifo_1_1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_1_1_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axis_data_fifo_1_1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_1_1_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_axis_data_fifo_2_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_2_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_axis_data_fifo_2_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_axis_data_fifo_2_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_processing_system7_0_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_processing_system7_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_processing_system7_0_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_processing_system7_0_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'USB0_PORT_INDCTL' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7071] port 'USB0_VBUS_PWRSELECT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_BID' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_RID' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_RCOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_WCOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_RACOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7071] port 'S_AXI_HP0_WACOUNT' of module 'design_a9_1_processing_system7_0_0' is unconnected for instance 'processing_system7_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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WARNING: [Synth 8-7023] instance 'processing_system7_0' of module 'design_a9_1_processing_system7_0_0' has 111 connections declared, but only 103 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2322]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_rst_ps7_0_50M_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_rst_ps7_0_50M_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_rst_ps7_0_50M_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_rst_ps7_0_50M_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'mb_reset' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2426]
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WARNING: [Synth 8-7071] port 'bus_struct_reset' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2426]
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WARNING: [Synth 8-7071] port 'peripheral_reset' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2426]
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WARNING: [Synth 8-7071] port 'interconnect_aresetn' of module 'design_a9_1_rst_ps7_0_50M_0' is unconnected for instance 'rst_ps7_0_50M' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2426]
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WARNING: [Synth 8-7023] instance 'rst_ps7_0_50M' of module 'design_a9_1_rst_ps7_0_50M_0' has 10 connections declared, but only 6 given [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:2426]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_smartconnect_0_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_smartconnect_0_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_smartconnect_0_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/design_a9_1_smartconnect_0_0_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'design_a9_1_xlconcat_0_0' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/synth/design_a9_1_xlconcat_0_0.v:53]
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INFO: [Synth 8-6157] synthesizing module 'xlconcat_v2_1_4_xlconcat' [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v:14]
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INFO: [Synth 8-6155] done synthesizing module 'xlconcat_v2_1_4_xlconcat' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ipshared/4b67/hdl/xlconcat_v2_1_vl_rfs.v:14]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_xlconcat_0_0' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_xlconcat_0_0/synth/design_a9_1_xlconcat_0_0.v:53]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/synth/design_a9_1.v:13]
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INFO: [Synth 8-6155] done synthesizing module 'design_a9_1_wrapper' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/hdl/design_a9_1_wrapper.v:13]
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INFO: [Synth 8-6157] synthesizing module 'pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:3]
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Parameter VERSION bound to: 536870917 - type: integer
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Parameter CLK_FREQ bound to: 100 - type: integer
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter RSH2116_QTY bound to: 2 - type: integer
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Parameter ADS1299_QTY bound to: 4 - type: integer
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Parameter ADS1299_SPI_QTY bound to: 4 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'eeg_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'ads1299_arrange' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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Parameter SPI_TRANS_PERIOD bound to: 2000 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_arrange' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ads1299_if' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v:3]
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Parameter SPI_CLK_DIV bound to: 3 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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Parameter SPI_SLAVE_QTY bound to: 2 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'ads1299_spi' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CLK_DIV bound to: 3 - type: integer
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Parameter DATA_WIDTH bound to: 8 - type: integer
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Parameter NO_OF_SLAVES bound to: 2 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_spi' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_if' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v:3]
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INFO: [Synth 8-6157] synthesizing module 'eeg_config' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v:3]
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Parameter SPIS_QTY bound to: 2 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'eeg_config' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v:3]
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INFO: [Synth 8-6157] synthesizing module 'eeg_upload' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CHIPSET_QTY bound to: 2 - type: integer
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Parameter CH_OF_CHIPSET bound to: 16 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'eeg_upload' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'eeg_top' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'eeg_top1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CHIPSET_QTY bound to: 1 - type: integer
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Parameter SPIS_QTY bound to: 1 - type: integer
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Parameter SPI_SLAVE_QTY bound to: 1 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'ads1299_if1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if1.v:3]
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Parameter SPI_CLK_DIV bound to: 3 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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Parameter SPI_SLAVE_QTY bound to: 1 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'ads1299_spi1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi1.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CLK_DIV bound to: 3 - type: integer
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Parameter DATA_WIDTH bound to: 8 - type: integer
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Parameter NO_OF_SLAVES bound to: 1 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_spi1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi1.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'ads1299_if1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/ads1299_if1.v:3]
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WARNING: [Synth 8-689] width (32) of port connection 'eeg_tr_array' does not match port width (64) of module 'eeg_config' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:123]
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INFO: [Synth 8-6157] synthesizing module 'eeg_upload__parameterized0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CHIPSET_QTY bound to: 1 - type: integer
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Parameter CH_OF_CHIPSET bound to: 8 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'eeg_upload__parameterized0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'eeg_top1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:3]
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INFO: [Synth 8-6157] synthesizing module 'cur_mon_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:3]
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Parameter CLK_PERIOD bound to: 500 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'ad7689_dual_if' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v:3]
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Parameter CLK_PERIOD bound to: 500 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'ad7689_dual_if' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_if.v:3]
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INFO: [Synth 8-6157] synthesizing module 'cur_mon_config' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v:3]
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Parameter CH_QTY bound to: 16 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'cur_mon_config' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v:3]
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INFO: [Synth 8-6157] synthesizing module 'ad7689_dual_ctrl' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v:3]
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Parameter CLK_PERIOD bound to: 500 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'ad7689_dual_ctrl' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/ad7689_dual_ctrl.v:3]
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INFO: [Synth 8-6157] synthesizing module 'acq_collect' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v:3]
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Parameter CLK_PERIOD bound to: 500 - type: integer
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Parameter SPI_QTY bound to: 2 - type: integer
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Parameter CH_OF_SPI bound to: 8 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'acq_collect' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v:3]
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INFO: [Synth 8-6157] synthesizing module 'cur_ch_map' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v:3]
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Parameter CLK_PERIOD bound to: 500 - type: integer
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Parameter CH_QTY bound to: 16 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'cur_ch_map' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_ch_map.v:3]
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INFO: [Synth 8-6157] synthesizing module 'cur_monitor' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v:3]
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Parameter CLK_PERIOD bound to: 500 - type: integer
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Parameter CH_QTY bound to: 16 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'c_add_s16_s32' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/c_add_s16_s32_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'c_add_s16_s32' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/c_add_s16_s32_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'cur_monitor' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v:3]
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WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:287]
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INFO: [Synth 8-6157] synthesizing module 'vio_cur_flt_state' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/vio_cur_flt_state_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'vio_cur_flt_state' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/vio_cur_flt_state_stub.v:6]
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INFO: [Synth 8-6157] synthesizing module 'fifo_generator_1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/fifo_generator_1_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'fifo_generator_1' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/fifo_generator_1_stub.v:6]
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WARNING: [Synth 8-7071] port 'wr_rst_busy' of module 'fifo_generator_1' is unconnected for instance 'u0_fifo_generator_1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:295]
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WARNING: [Synth 8-7071] port 'rd_rst_busy' of module 'fifo_generator_1' is unconnected for instance 'u0_fifo_generator_1' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:295]
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WARNING: [Synth 8-7023] instance 'u0_fifo_generator_1' of module 'fifo_generator_1' has 11 connections declared, but only 9 given [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:295]
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INFO: [Synth 8-6155] done synthesizing module 'cur_mon_top' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:3]
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WARNING: [Synth 8-689] width (1) of port connection 'cnv' does not match port width (2) of module 'cur_mon_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:512]
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WARNING: [Synth 8-689] width (1) of port connection 'sck' does not match port width (2) of module 'cur_mon_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:513]
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WARNING: [Synth 8-689] width (1) of port connection 'mosi' does not match port width (2) of module 'cur_mon_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:514]
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WARNING: [Synth 8-689] width (1) of port connection 'debug_sig' does not match port width (4) of module 'cur_mon_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:521]
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INFO: [Synth 8-6157] synthesizing module 'accel_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/accel/accel_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'accel_top' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/accel/accel_top.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'run_time' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/run_time.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'run_time' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/run_time.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_config' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_config.v:3]
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Parameter CHANNLE_QTY bound to: 64 - type: integer
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Parameter PRE_MSG_LEN bound to: 128 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'upload_config' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_config.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_sort' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter CHANNLE_QTY bound to: 64 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'axis_data_fifo_w8_d128' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/axis_data_fifo_w8_d128_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'axis_data_fifo_w8_d128' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/axis_data_fifo_w8_d128_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'upload_sort' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v:3]
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INFO: [Synth 8-6157] synthesizing module 'upload_protocol_ql' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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Parameter PRE_MSG_LEN bound to: 128 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'upload_protocol_ql' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v:3]
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WARNING: [Synth 8-7071] port 'interrupt' of module 'upload_protocol_ql' is unconnected for instance 'u_upload_protocol_ql' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:200]
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WARNING: [Synth 8-7023] instance 'u_upload_protocol_ql' of module 'upload_protocol_ql' has 25 connections declared, but only 24 given [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:200]
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INFO: [Synth 8-6157] synthesizing module 'upload_protocol_intan' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'upload_protocol_intan' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'upload_top' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:3]
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WARNING: [Synth 8-7071] port 'interrupt' of module 'upload_top' is unconnected for instance 'u0_upload_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:610]
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WARNING: [Synth 8-7023] instance 'u0_upload_top' of module 'upload_top' has 33 connections declared, but only 32 given [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:610]
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WARNING: [Synth 8-7071] port 'interrupt' of module 'upload_top' is unconnected for instance 'u1_upload_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:662]
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WARNING: [Synth 8-7023] instance 'u1_upload_top' of module 'upload_top' has 33 connections declared, but only 32 given [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:662]
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INFO: [Synth 8-6157] synthesizing module 'eeg_emg_upload' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v:3]
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INFO: [Synth 8-6157] synthesizing module 'fifo_generator_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/fifo_generator_0_stub.v:6]
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INFO: [Synth 8-6155] done synthesizing module 'fifo_generator_0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/.Xil/Vivado-8436-DESKTOP-VN054CM/realtime/fifo_generator_0_stub.v:6]
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WARNING: [Synth 8-7071] port 'wr_rst_busy' of module 'fifo_generator_0' is unconnected for instance 'u0_fifo_generator_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v:354]
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WARNING: [Synth 8-7071] port 'rd_rst_busy' of module 'fifo_generator_0' is unconnected for instance 'u0_fifo_generator_0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v:354]
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WARNING: [Synth 8-7023] instance 'u0_fifo_generator_0' of module 'fifo_generator_0' has 11 connections declared, but only 9 given [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v:354]
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INFO: [Synth 8-6155] done synthesizing module 'eeg_emg_upload' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v:3]
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INFO: [Synth 8-6157] synthesizing module 'stim_config' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/stim_config.v:3]
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Parameter SPIS_QTY bound to: 4 - type: integer
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Parameter SPI_DATA_WIDTH bound to: 8 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'stim_config' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/stim_config.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'pl_top' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:3]
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WARNING: [Synth 8-689] width (4) of port connection 'eeg_ads1299_spi_sclk' does not match port width (2) of module 'pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:598]
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WARNING: [Synth 8-689] width (4) of port connection 'eeg_ads1299_spi_mosi' does not match port width (2) of module 'pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:599]
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WARNING: [Synth 8-689] width (4) of port connection 'eeg_ads1299_spi_miso' does not match port width (2) of module 'pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:600]
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WARNING: [Synth 8-7071] port 'rsh2116_enable' of module 'pl_top' is unconnected for instance 'u_pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:497]
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WARNING: [Synth 8-7071] port 'rsh2116_spi_cs' of module 'pl_top' is unconnected for instance 'u_pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:497]
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WARNING: [Synth 8-7071] port 'rsh2116_spi_sclk' of module 'pl_top' is unconnected for instance 'u_pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:497]
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WARNING: [Synth 8-7071] port 'rsh2116_spi_mosi' of module 'pl_top' is unconnected for instance 'u_pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:497]
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WARNING: [Synth 8-7071] port 'rsh2116_spi_miso' of module 'pl_top' is unconnected for instance 'u_pl_top' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:497]
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WARNING: [Synth 8-7023] instance 'u_pl_top' of module 'pl_top' has 103 connections declared, but only 98 given [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:497]
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INFO: [Synth 8-6157] synthesizing module 'led_ctrl' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/led_ctrl.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'pwm_gen' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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Parameter DATA_WIDTH bound to: 28 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'pwm_gen' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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INFO: [Synth 8-6157] synthesizing module 'breath_gen' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v:3]
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Parameter CLK_PERIOD bound to: 10 - type: integer
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INFO: [Synth 8-6157] synthesizing module 'pwm_gen__parameterized0' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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Parameter DATA_WIDTH bound to: 16 - type: integer
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INFO: [Synth 8-6155] done synthesizing module 'pwm_gen__parameterized0' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/pwm_gen.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'breath_gen' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/utils/breath_gen.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'led_ctrl' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/led_ctrl.v:3]
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INFO: [Synth 8-6155] done synthesizing module 'c64pro_top' (0#1) [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:3]
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WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v:96]
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WARNING: [Synth 8-3848] Net eeg_sr in module/entity eeg_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v:55]
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WARNING: [Synth 8-3848] Net eeg_sr in module/entity eeg_top1 does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/eeg/eeg_top1.v:55]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'acquisition[0].u_ad7689_dual_if'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:196]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'acquisition[1].u_ad7689_dual_if'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:196]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_cur_mon_config'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:140]
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WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v:206]
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WARNING: [Synth 8-6014] Unused sequential element n_reg was removed. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_config.v:217]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_ad7689_dual_ctrl'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:179]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_acq_collect'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:223]
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WARNING: [Synth 8-6014] Unused sequential element rx_data[0].s_axis_tlast_r_reg[0] was removed. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/acq_collect.v:53]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_cur_ch_map'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:242]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_add_total'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v:81]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_add_negative'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v:101]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_add_positive'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_monitor.v:91]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_cur_mon_top'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:495]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u0_fifo_generator_1'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:295]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_cur_monitor'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:262]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_vio_cur_flt_state'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/current_monitor/cur_mon_top.v:287]
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WARNING: [Synth 8-3848] Net s_axis_emg_tready in module/entity upload_sort does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v:25]
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WARNING: [Synth 8-3848] Net interrupt in module/entity upload_protocol_ql does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v:14]
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WARNING: [Synth 8-3848] Net interrupt in module/entity upload_protocol_intan does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v:13]
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WARNING: [Synth 8-3848] Net interrupt in module/entity upload_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:21]
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WARNING: [Synth 8-3848] Net debug_sig in module/entity upload_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/upload_top.v:51]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_eeg_emg_upload'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:710]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u0_fifo_generator_0'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/upload/eeg_emg_upload.v:354]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_stim_config'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:780]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u_pl_top'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:497]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u1_eeg_top'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:456]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u0_eeg_top'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:415]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u0_upload_top'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:610]
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INFO: [Synth 8-6071] Mark debug on the nets applies keep_hierarchy on instance 'u1_upload_top'. This will prevent further optimization [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:662]
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WARNING: [Synth 8-3848] Net bram_stim_dout in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:34]
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WARNING: [Synth 8-3848] Net stim_int in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:96]
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WARNING: [Synth 8-3848] Net m_axis_stim_tready in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:103]
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WARNING: [Synth 8-3848] Net rsh2116_enable in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:119]
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WARNING: [Synth 8-3848] Net rsh2116_spi_cs in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:120]
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WARNING: [Synth 8-3848] Net rsh2116_spi_sclk in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:121]
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WARNING: [Synth 8-3848] Net rsh2116_spi_mosi in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:122]
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WARNING: [Synth 8-3848] Net debug_sig_2116 in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:229]
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WARNING: [Synth 8-3848] Net sw_data_1 in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:226]
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WARNING: [Synth 8-3848] Net accel_spi_miso in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:548]
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WARNING: [Synth 8-3848] Net accel_int0 in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:549]
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WARNING: [Synth 8-3848] Net accel_int1 in module/entity pl_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:550]
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WARNING: [Synth 8-3848] Net led_cmd_wifi in module/entity c64pro_top does not have driver. [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/c64pro_top.v:289]
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WARNING: [Synth 8-7129] Port bram_clk in module stim_config is either unconnected or has no load
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WARNING: [Synth 8-7129] Port bram_rst in module stim_config is either unconnected or has no load
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WARNING: [Synth 8-7129] Port interrupt in module upload_protocol_intan is either unconnected or has no load
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WARNING: [Synth 8-7129] Port interrupt in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[215] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[214] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[213] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[212] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[211] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[210] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[209] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[208] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[207] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[206] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[205] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[204] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[203] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[202] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[201] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[200] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[199] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[198] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[197] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[196] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[195] in module upload_protocol_ql is either unconnected or has no load
|
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WARNING: [Synth 8-7129] Port pre_message_array[194] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[193] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[192] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[191] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[190] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[189] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[188] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[187] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[186] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[185] in module upload_protocol_ql is either unconnected or has no load
|
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WARNING: [Synth 8-7129] Port pre_message_array[184] in module upload_protocol_ql is either unconnected or has no load
|
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WARNING: [Synth 8-7129] Port pre_message_array[175] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[174] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[173] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[172] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[171] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[170] in module upload_protocol_ql is either unconnected or has no load
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WARNING: [Synth 8-7129] Port pre_message_array[169] in module upload_protocol_ql is either unconnected or has no load
|
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WARNING: [Synth 8-7129] Port pre_message_array[168] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[167] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[166] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[165] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[164] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[163] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[162] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[161] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[160] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[159] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[158] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[157] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[156] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[155] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[154] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[153] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[152] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[151] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[150] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[149] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[148] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[147] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[146] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[145] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[144] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[143] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[142] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[141] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[140] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[139] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[138] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[137] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[136] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[135] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[134] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[133] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[132] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[131] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[130] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[129] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[128] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[127] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[126] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[125] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[124] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[123] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[122] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[121] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[120] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[119] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[118] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[117] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[116] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[115] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[114] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[113] in module upload_protocol_ql is either unconnected or has no load
|
|
WARNING: [Synth 8-7129] Port pre_message_array[112] in module upload_protocol_ql is either unconnected or has no load
|
|
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2794.930 ; gain = 739.629
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2812.742 ; gain = 757.441
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2812.742 ; gain = 757.441
|
|
---------------------------------------------------------------------------------
|
|
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.493 . Memory (MB): peak = 2824.781 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 27 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
|
|
Processing XDC Constraints
|
|
Initializing timing engine
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_1_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_2_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_3_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_4_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0/design_a9_1_axi_dma_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0/design_a9_1_axi_dma_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_1'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0/design_a9_1_axi_gpio_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_gpio_0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0/design_a9_1_axi_smc_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_smc'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0/design_a9_1_axis_data_fifo_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0/design_a9_1_axis_data_fifo_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_1'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/processing_system7_0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0/design_a9_1_rst_ps7_0_50M_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0/design_a9_1_smartconnect_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/smartconnect_0'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_1_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_0/design_a9_1_axi_gpio_1_1_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_EN'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0/design_a9_1_axi_gpio_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_0/design_a9_1_CHANN_EN_0/design_a9_1_axi_gpio_1_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CHANN_SEL'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0/design_a9_1_CHANN_SEL_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/RST_AD5941'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0/design_a9_1_ZCHECK_SPI_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_quad_spi_0_0/design_a9_1_axi_quad_spi_0_0/design_a9_1_ZCHECK_SPI_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI'
|
|
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO'
|
|
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1/design_a9_1_CHANN_EN_1_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/Z_IO'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_3_1/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2/design_a9_1_CHANN_EN_2_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_2'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_1_1/design_a9_1_axis_data_fifo_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_2'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_1_1/design_a9_1_axi_dma_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_2'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0/design_a9_1_axi_dma_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_dma_3'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_3'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0/design_a9_1_axis_data_fifo_2_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axis_data_fifo_3'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0/design_a9_1_STIM_SPI_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_ZCHECK_SPI_0/design_a9_1_ZCHECK_SPI_0/design_a9_1_STIM_SPI_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/STIM_SPI'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0/design_a9_1_CHANN_EN_1_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_Z_IO_0/design_a9_1_Z_IO_0/design_a9_1_CHANN_EN_1_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/GPIO'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_5_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_6_0/design_a9_1_axi_bram_ctrl_0_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0/design_a9_1_STIM_SPI_0_in_context.xdc] for cell 'u_ps_a9_1/design_a9_1_i/CUR_SPI'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_in_context.xdc] for cell 'u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_in_context.xdc] for cell 'u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_in_context.xdc] for cell 'u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128/axis_data_fifo_w8_d128_in_context.xdc] for cell 'u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_in_context.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/ip/fifo_generator_0/fifo_generator_0/fifo_generator_0_in_context.xdc] for cell 'u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1/fifo_generator_1_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/fifo_generator_1/fifo_generator_1/fifo_generator_1_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u0_fifo_generator_1'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state/vio_cur_flt_state_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/vio_cur_flt_state/vio_cur_flt_state/vio_cur_flt_state_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_vio_cur_flt_state'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32/c_add_s16_s32_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_total'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32/c_add_s16_s32_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_total'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32/c_add_s16_s32_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_positive'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32/c_add_s16_s32_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_positive'
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Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32/c_add_s16_s32_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative'
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Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v10/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32/c_add_s16_s32_in_context.xdc] for cell 'u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative'
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ads1299_emg.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]
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INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/constrs_1/new/c64pro_pins_ic.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/c64pro_top_propImpl.xdc].
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Resolution: To avoid this warning, move constraints listed in [.Xil/c64pro_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
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Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/dont_touch.xdc]
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Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/dont_touch.xdc]
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Completed Processing XDC Constraints
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Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.020 . Memory (MB): peak = 2927.488 ; gain = 0.000
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INFO: [Project 1-111] Unisim Transformation Summary:
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A total of 27 instances were transformed.
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IOBUF => IOBUF (IBUF, OBUFT): 27 instances
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Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.263 . Memory (MB): peak = 2927.488 ; gain = 0.000
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WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'u_ps_a9_1/design_a9_1_i/CUR_SPI' at clock pin 'ext_spi_clk' is different from the actual clock period '10.000', this can lead to different synthesis results.
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WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'u_ps_a9_1/design_a9_1_i/STIM_SPI' at clock pin 'ext_spi_clk' is different from the actual clock period '10.000', this can lead to different synthesis results.
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WARNING: [Timing 38-316] Clock period '20.000' specified during out-of-context synthesis of instance 'u_ps_a9_1/design_a9_1_i/ZCHECK_SPI' at clock pin 'ext_spi_clk' is different from the actual clock period '10.000', this can lead to different synthesis results.
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---------------------------------------------------------------------------------
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Finished Constraint Validation : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2927.492 ; gain = 872.191
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Loading Part and Timing Information
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---------------------------------------------------------------------------------
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Loading part: xc7z020clg400-2
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---------------------------------------------------------------------------------
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Finished Loading Part and Timing Information : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2927.492 ; gain = 872.191
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---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
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Start Applying 'set_property' XDC Constraints
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---------------------------------------------------------------------------------
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 2).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 3).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 4).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 5).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 6).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 7).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 8).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 9).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 10).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 11).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 12).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 13).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 14).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 15).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 16).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 17).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 18).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 19).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 20).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 21).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 22).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 23).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 24).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 25).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 26).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 27).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 28).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 29).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 30).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 31).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 32).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 33).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 34).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 35).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 36).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 37).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 38).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 39).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 40).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 41).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 42).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 43).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 44).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 45).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 46).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 47).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 48).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 49).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 50).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 51).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 52).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 53).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 54).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 55).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 56).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 57).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 58).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 59).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 60).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 61).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 62).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 63).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 64).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 65).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 66).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 67).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 68).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 69).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 70).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 71).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 72).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 73).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 74).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 75).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 76).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 77).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 78).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 79).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 80).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 81).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 82).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 83).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 84).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 85).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 86).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 87).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 88).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 89).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 90).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 91).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 92).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 93).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 94).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 95).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 96).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 97).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 98).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 99).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 100).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 101).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 102).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 103).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 104).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 105).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 106).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 107).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 108).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 109).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 110).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 111).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 112).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 113).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 114).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 115).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 116).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 117).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 118).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 119).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 120).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 121).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 122).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 123).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 124).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 125).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 126).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 127).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 128).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 129).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 130).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 131).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 132).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 133).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 134).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 135).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 136).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 137).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 138).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 139).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 140).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 141).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 142).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 143).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 144).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 145).
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Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 146).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 147).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 148).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 149).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 150).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 151).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 152).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 153).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 154).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 155).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 156).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 157).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 158).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 159).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 160).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 161).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 162).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 163).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 164).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 165).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 166).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 167).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 168).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 169).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 170).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 171).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 172).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 173).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 174).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 175).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 176).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 177).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 178).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 179).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 180).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 181).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 182).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 183).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 184).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 185).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 186).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 187).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 188).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 189).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 190).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 191).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 192).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 193).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 194).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 195).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 196).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 197).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 198).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 199).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 200).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 201).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 202).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 203).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 204).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 205).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 206).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 207).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 208).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 209).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 210).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 211).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 212).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 213).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 214).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 215).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 216).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 217).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 218).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 219).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 220).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 221).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 222).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 223).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 224).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 225).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 226).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 227).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 228).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 229).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 230).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 231).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 232).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 233).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 234).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 235).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 236).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 237).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 238).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 239).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 240).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 241).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 242).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 243).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 244).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 245).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 246).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 247).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 248).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 249).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 250).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 251).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 252).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 253).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 254).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 255).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 256).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 257).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 258).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 259).
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Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 260).
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Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file d:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.gen/sources_1/bd/design_a9_1/ip/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0/design_a9_1_processing_system7_0_0_in_context.xdc, line 261).
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Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i. (constraint file auto generated constraint).
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Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_0. (constraint file auto generated constraint).
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Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_1. (constraint file auto generated constraint).
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Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_2. (constraint file auto generated constraint).
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Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_3. (constraint file auto generated constraint).
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Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_4. (constraint file auto generated constraint).
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Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_dma_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_dma_1. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_gpio_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_smc. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axis_data_fifo_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axis_data_fifo_1. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/processing_system7_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/smartconnect_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/xlconcat_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/CHANN_EN. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/CHANN_SEL. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/RST_AD5941. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/ZCHECK_SPI. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/Z_IO. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_5. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/ELEC_MUX_IN. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axis_data_fifo_2. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_dma_2. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_dma_3. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axis_data_fifo_3. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/STIM_SPI. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/GPIO. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_6. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/axi_bram_ctrl_7. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_ps_a9_1/design_a9_1_i/CUR_SPI. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u0_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u1_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_eeg_emg_upload/u0_fifo_generator_0. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_cur_mon_top/u0_fifo_generator_1. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_cur_mon_top/u_vio_cur_flt_state. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_negative. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_positive. (constraint file auto generated constraint).
|
|
Applied set_property KEEP_HIERARCHY = SOFT for u_pl_top/u_cur_mon_top/u_cur_monitor/u_add_total. (constraint file auto generated constraint).
|
|
---------------------------------------------------------------------------------
|
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:37 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'ads1299_arrange'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'ads1299_spi'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'eeg_upload'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'ads1299_spi1'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'eeg_upload__parameterized0'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'ad7689_dual_if'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'acq_collect'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'upload_sort__xdcDup__1'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'upload_protocol_ql'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'upload_protocol_intan'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'upload_sort'
|
|
INFO: [Synth 8-802] inferred FSM for state register 'cstate_reg' in module 'breath_gen'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 000 | 0000
|
|
TRANS_ST | 101 | 0001
|
|
WAIT_ST | 100 | 0010
|
|
RDATAC_ST | 010 | 0011
|
|
REVC_1_ST | 011 | 0100
|
|
REVC_2_ST | 001 | 0101
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'ads1299_arrange'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 0001 | 0000
|
|
TRANS_ST | 1000 | 0001
|
|
SCCS_ST | 0100 | 0010
|
|
CSH_ST | 0010 | 0011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'ads1299_spi'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 001 | 0000
|
|
READY_ST | 100 | 0001
|
|
SCAN_ST | 010 | 0010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'eeg_upload'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 00 | 0000
|
|
TRANS_ST | 11 | 0001
|
|
SCCS_ST | 10 | 0010
|
|
CSH_ST | 01 | 0011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'ads1299_spi1'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 001 | 0000
|
|
READY_ST | 010 | 0001
|
|
SCAN_ST | 100 | 0010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'eeg_upload__parameterized0'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 001 | 0000
|
|
TRANS_ST | 010 | 0001
|
|
END_ST | 100 | 0010
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'ad7689_dual_if'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 0 | 0000
|
|
SCAN_ST | 1 | 0001
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'acq_collect'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
ST_IDLE | 0001 | 0000
|
|
ST_RX | 0010 | 0001
|
|
ST_SCAN | 0100 | 0010
|
|
ST_TX | 1000 | 0011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'upload_sort__xdcDup__1'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
ST_IDLE | 000 | 0000
|
|
ST_MSG_HEAD | 111 | 0001
|
|
ST_WAIT | 010 | 0010
|
|
ST_MSG_CRC | 011 | 0110
|
|
ST_ADDITIONAL | 001 | 0111
|
|
ST_READ_TRIGGER | 110 | 0011
|
|
ST_MSG_TRIGGER | 101 | 0100
|
|
ST_MSG_RECORD | 100 | 0101
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'upload_protocol_ql'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
ST_IDLE | 000000010000 | 0000
|
|
ST_MSG_HEAD | 000000001000 | 0010
|
|
ST_MSG_DATA_H | 000000000001 | 0011
|
|
ST_MSG_RECORD | 000000000010 | 0100
|
|
ST_MSG_DATA_T | 000000000100 | 0101
|
|
ST_MSG_REG_VAL | 100000000000 | 0110
|
|
ST_MSG_DA_AD | 000100000000 | 0111
|
|
ST_MSG_TRIG_IN | 001000000000 | 1000
|
|
ST_MSG_TRIG_OUT | 010000000000 | 1001
|
|
ST_WAIT | 000001000000 | 0001
|
|
ST_MSG_CRC | 000010000000 | 1010
|
|
ST_ADDITIONAL | 000000100000 | 1011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'upload_protocol_intan'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
ST_IDLE | 0001 | 0000
|
|
ST_RX | 0010 | 0001
|
|
ST_SCAN | 0100 | 0010
|
|
ST_TX | 1000 | 0011
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'one-hot' in module 'upload_sort'
|
|
---------------------------------------------------------------------------------------------------
|
|
State | New Encoding | Previous Encoding
|
|
---------------------------------------------------------------------------------------------------
|
|
IDLE | 000 | 0000
|
|
UP_ST | 001 | 0001
|
|
PEAK_ST | 010 | 0010
|
|
DOWN_ST | 011 | 0011
|
|
REST_ST | 100 | 0100
|
|
---------------------------------------------------------------------------------------------------
|
|
INFO: [Synth 8-3354] encoded FSM with state register 'cstate_reg' using encoding 'sequential' in module 'breath_gen'
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:43 ; elapsed = 00:00:45 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
Detailed RTL Component Info :
|
|
+---Adders :
|
|
2 Input 32 Bit Adders := 22
|
|
2 Input 28 Bit Adders := 2
|
|
2 Input 20 Bit Adders := 2
|
|
2 Input 16 Bit Adders := 32
|
|
2 Input 10 Bit Adders := 1
|
|
2 Input 9 Bit Adders := 5
|
|
2 Input 8 Bit Adders := 38
|
|
2 Input 4 Bit Adders := 7
|
|
2 Input 3 Bit Adders := 4
|
|
+---XORs :
|
|
2 Input 1 Bit XORs := 51
|
|
6 Input 1 Bit XORs := 5
|
|
4 Input 1 Bit XORs := 12
|
|
7 Input 1 Bit XORs := 4
|
|
3 Input 1 Bit XORs := 29
|
|
5 Input 1 Bit XORs := 5
|
|
+---Registers :
|
|
64 Bit Registers := 2
|
|
32 Bit Registers := 194
|
|
28 Bit Registers := 3
|
|
24 Bit Registers := 5
|
|
20 Bit Registers := 2
|
|
16 Bit Registers := 68
|
|
14 Bit Registers := 1
|
|
10 Bit Registers := 1
|
|
9 Bit Registers := 5
|
|
8 Bit Registers := 494
|
|
4 Bit Registers := 11
|
|
3 Bit Registers := 4
|
|
2 Bit Registers := 5
|
|
1 Bit Registers := 157
|
|
+---Muxes :
|
|
2 Input 64 Bit Muxes := 2
|
|
2 Input 32 Bit Muxes := 42
|
|
7 Input 32 Bit Muxes := 1
|
|
3 Input 32 Bit Muxes := 2
|
|
2 Input 28 Bit Muxes := 4
|
|
2 Input 24 Bit Muxes := 1
|
|
2 Input 20 Bit Muxes := 2
|
|
2 Input 16 Bit Muxes := 43
|
|
12 Input 12 Bit Muxes := 2
|
|
2 Input 12 Bit Muxes := 28
|
|
2 Input 10 Bit Muxes := 1
|
|
2 Input 9 Bit Muxes := 8
|
|
2 Input 8 Bit Muxes := 1046
|
|
4 Input 8 Bit Muxes := 9
|
|
3 Input 8 Bit Muxes := 8
|
|
7 Input 8 Bit Muxes := 2
|
|
2 Input 6 Bit Muxes := 2
|
|
2 Input 4 Bit Muxes := 57
|
|
4 Input 4 Bit Muxes := 4
|
|
8 Input 4 Bit Muxes := 2
|
|
12 Input 4 Bit Muxes := 14
|
|
5 Input 4 Bit Muxes := 1
|
|
2 Input 3 Bit Muxes := 99
|
|
8 Input 3 Bit Muxes := 12
|
|
3 Input 3 Bit Muxes := 16
|
|
6 Input 3 Bit Muxes := 15
|
|
7 Input 3 Bit Muxes := 1
|
|
5 Input 3 Bit Muxes := 1
|
|
12 Input 3 Bit Muxes := 1
|
|
2 Input 2 Bit Muxes := 97
|
|
3 Input 2 Bit Muxes := 21
|
|
4 Input 2 Bit Muxes := 22
|
|
5 Input 2 Bit Muxes := 1
|
|
2 Input 1 Bit Muxes := 436
|
|
3 Input 1 Bit Muxes := 21
|
|
5 Input 1 Bit Muxes := 256
|
|
7 Input 1 Bit Muxes := 4
|
|
4 Input 1 Bit Muxes := 4
|
|
8 Input 1 Bit Muxes := 1
|
|
---------------------------------------------------------------------------------
|
|
Finished RTL Component Statistics
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
Part Resources:
|
|
DSPs: 220 (col length:60)
|
|
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
|
|
---------------------------------------------------------------------------------
|
|
Finished Part Resource Summary
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Cross Boundary and Area Optimization
|
|
---------------------------------------------------------------------------------
|
|
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
|
---------------------------------------------------------------------------------
|
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:51 ; elapsed = 00:02:55 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
|
|
ROM: Preliminary Mapping Report
|
|
+------------+--------------+---------------+----------------+
|
|
|Module Name | RTL Object | Depth x Width | Implemented As |
|
|
+------------+--------------+---------------+----------------+
|
|
|upload_sort | ch_map2intan | 64x6 | LUT |
|
|
|upload_sort | ch_map2intan | 64x6 | LUT |
|
|
|upload_sort | ch_map2intan | 64x6 | LUT |
|
|
|upload_sort | ch_map2intan | 64x6 | LUT |
|
|
+------------+--------------+---------------+----------------+
|
|
|
|
---------------------------------------------------------------------------------
|
|
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Applying XDC Timing Constraints
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:00 ; elapsed = 00:03:03 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Timing Optimization
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Timing Optimization : Time (s): cpu = 00:03:10 ; elapsed = 00:03:13 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Technology Mapping
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Technology Mapping : Time (s): cpu = 00:03:22 ; elapsed = 00:03:26 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Flattening Before IO Insertion
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Final Netlist Cleanup
|
|
---------------------------------------------------------------------------------
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[31] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[30] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[29] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[28] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[27] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[26] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[25] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[24] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[23] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[22] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[21] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[20] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[19] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[18] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[17] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[16] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[15] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[14] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[13] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[12] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[11] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[10] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[9] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[8] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[7] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[6] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[5] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[4] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[3] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[2] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[1] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tdata_inferred:in0[0] to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tlast_inferred:in0 to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tready_inferred:in0 to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin axis_eeg16_tvalid_inferred:in0 to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin adgs5414_start_inferred:in0 to constant 0
|
|
WARNING: [Synth 8-3295] tying undriven pin adgs5414_start2_inferred:in0 to constant 0
|
|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[3] with 1st driver pin 'u_pl_top/u0_eeg_top/debug_sig[3]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:415]
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|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[3] with 2nd driver pin 'u_pl_top/u1_eeg_top/debug_sig[3]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:456]
|
|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[2] with 1st driver pin 'u_pl_top/u0_eeg_top/debug_sig[2]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:415]
|
|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[2] with 2nd driver pin 'u_pl_top/u1_eeg_top/debug_sig[2]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:456]
|
|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[1] with 1st driver pin 'u_pl_top/u0_eeg_top/debug_sig[1]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:415]
|
|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[1] with 2nd driver pin 'u_pl_top/u1_eeg_top/debug_sig[1]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:456]
|
|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[0] with 1st driver pin 'u_pl_top/u0_eeg_top/debug_sig[0]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:415]
|
|
WARNING: [Synth 8-5753] loadless multi-driven net debug_sig_eeg[0] with 2nd driver pin 'u_pl_top/u1_eeg_top/debug_sig[0]' [D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.srcs/sources_1/rtl/pl_top.v:456]
|
|
---------------------------------------------------------------------------------
|
|
Finished IO Insertion : Time (s): cpu = 00:03:28 ; elapsed = 00:03:31 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Instances
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Instances : Time (s): cpu = 00:03:28 ; elapsed = 00:03:31 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Rebuilding User Hierarchy
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:30 ; elapsed = 00:03:33 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Ports
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Ports : Time (s): cpu = 00:03:30 ; elapsed = 00:03:33 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Handling Custom Attributes
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Handling Custom Attributes : Time (s): cpu = 00:03:30 ; elapsed = 00:03:34 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Renaming Generated Nets
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Finished Renaming Generated Nets : Time (s): cpu = 00:03:30 ; elapsed = 00:03:34 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
---------------------------------------------------------------------------------
|
|
Start Writing Synthesis Report
|
|
---------------------------------------------------------------------------------
|
|
|
|
Report BlackBoxes:
|
|
+------+-----------------------------------+----------+
|
|
| |BlackBox name |Instances |
|
|
+------+-----------------------------------+----------+
|
|
|1 |axis_data_fifo_w8_d128 | 2|
|
|
|2 |c_add_s16_s32 | 3|
|
|
|3 |vio_cur_flt_state | 1|
|
|
|4 |fifo_generator_1 | 1|
|
|
|5 |fifo_generator_0 | 1|
|
|
|6 |design_a9_1_axi_gpio_1_0 | 1|
|
|
|7 |design_a9_1_CHANN_EN_0 | 1|
|
|
|8 |design_a9_1_STIM_SPI_0 | 1|
|
|
|9 |design_a9_1_CHANN_EN_2 | 1|
|
|
|10 |design_a9_1_Z_IO_0 | 1|
|
|
|11 |design_a9_1_CHANN_SEL_0 | 1|
|
|
|12 |design_a9_1_ZCHECK_SPI_0 | 1|
|
|
|13 |design_a9_1_axi_quad_spi_0_0 | 1|
|
|
|14 |design_a9_1_CHANN_EN_1 | 1|
|
|
|15 |design_a9_1_axi_bram_ctrl_0_0 | 1|
|
|
|16 |design_a9_1_axi_bram_ctrl_1_0 | 1|
|
|
|17 |design_a9_1_axi_bram_ctrl_2_0 | 1|
|
|
|18 |design_a9_1_axi_bram_ctrl_3_0 | 1|
|
|
|19 |design_a9_1_axi_bram_ctrl_4_0 | 1|
|
|
|20 |design_a9_1_axi_bram_ctrl_3_1 | 1|
|
|
|21 |design_a9_1_axi_bram_ctrl_5_0 | 1|
|
|
|22 |design_a9_1_axi_bram_ctrl_6_0 | 1|
|
|
|23 |design_a9_1_axi_dma_0_0 | 1|
|
|
|24 |design_a9_1_axi_dma_1_0 | 1|
|
|
|25 |design_a9_1_axi_dma_1_1 | 1|
|
|
|26 |design_a9_1_axi_dma_2_0 | 1|
|
|
|27 |design_a9_1_axi_gpio_0_0 | 1|
|
|
|28 |design_a9_1_axi_smc_0 | 1|
|
|
|29 |design_a9_1_axis_data_fifo_0_0 | 1|
|
|
|30 |design_a9_1_axis_data_fifo_1_0 | 1|
|
|
|31 |design_a9_1_axis_data_fifo_1_1 | 1|
|
|
|32 |design_a9_1_axis_data_fifo_2_0 | 1|
|
|
|33 |design_a9_1_processing_system7_0_0 | 1|
|
|
|34 |design_a9_1_rst_ps7_0_50M_0 | 1|
|
|
|35 |design_a9_1_smartconnect_0_0 | 1|
|
|
+------+-----------------------------------+----------+
|
|
|
|
Report Cell Usage:
|
|
+------+---------------------------------+------+
|
|
| |Cell |Count |
|
|
+------+---------------------------------+------+
|
|
|1 |axis_data_fifo_w8_d128 | 2|
|
|
|3 |c_add_s16_s32 | 3|
|
|
|6 |design_a9_1_CHANN_EN | 3|
|
|
|9 |design_a9_1_CHANN_SEL | 1|
|
|
|10 |design_a9_1_STIM_SPI | 1|
|
|
|11 |design_a9_1_ZCHECK_SPI | 1|
|
|
|12 |design_a9_1_Z_IO | 1|
|
|
|13 |design_a9_1_axi_bram_ctrl_0 | 1|
|
|
|14 |design_a9_1_axi_bram_ctrl_1 | 1|
|
|
|15 |design_a9_1_axi_bram_ctrl_2 | 1|
|
|
|16 |design_a9_1_axi_bram_ctrl_3 | 2|
|
|
|18 |design_a9_1_axi_bram_ctrl_4 | 1|
|
|
|19 |design_a9_1_axi_bram_ctrl_5 | 1|
|
|
|20 |design_a9_1_axi_bram_ctrl_6 | 1|
|
|
|21 |design_a9_1_axi_dma_0 | 1|
|
|
|22 |design_a9_1_axi_dma_1 | 2|
|
|
|24 |design_a9_1_axi_dma_2 | 1|
|
|
|25 |design_a9_1_axi_gpio_0 | 1|
|
|
|26 |design_a9_1_axi_gpio_1 | 1|
|
|
|27 |design_a9_1_axi_quad_spi_0 | 1|
|
|
|28 |design_a9_1_axi_smc | 1|
|
|
|29 |design_a9_1_axis_data_fifo_0 | 1|
|
|
|30 |design_a9_1_axis_data_fifo_1 | 2|
|
|
|32 |design_a9_1_axis_data_fifo_2 | 1|
|
|
|33 |design_a9_1_processing_system7_0 | 1|
|
|
|34 |design_a9_1_rst_ps7_0_50M | 1|
|
|
|35 |design_a9_1_smartconnect_0 | 1|
|
|
|36 |fifo_generator | 2|
|
|
|38 |vio_cur_flt_state | 1|
|
|
|39 |CARRY4 | 436|
|
|
|40 |LUT1 | 653|
|
|
|41 |LUT2 | 1186|
|
|
|42 |LUT3 | 794|
|
|
|43 |LUT4 | 541|
|
|
|44 |LUT5 | 783|
|
|
|45 |LUT6 | 4593|
|
|
|46 |MUXF7 | 1594|
|
|
|47 |MUXF8 | 712|
|
|
|48 |FDCE | 11681|
|
|
|49 |FDPE | 49|
|
|
|50 |FDRE | 9|
|
|
|51 |FDSE | 64|
|
|
|52 |IBUF | 5|
|
|
|53 |IOBUF | 27|
|
|
|54 |OBUF | 26|
|
|
+------+---------------------------------+------+
|
|
---------------------------------------------------------------------------------
|
|
Finished Writing Synthesis Report : Time (s): cpu = 00:03:30 ; elapsed = 00:03:34 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
---------------------------------------------------------------------------------
|
|
Synthesis finished with 0 errors, 0 critical warnings and 190 warnings.
|
|
Synthesis Optimization Runtime : Time (s): cpu = 00:03:04 ; elapsed = 00:03:25 . Memory (MB): peak = 2927.492 ; gain = 757.441
|
|
Synthesis Optimization Complete : Time (s): cpu = 00:03:30 ; elapsed = 00:03:34 . Memory (MB): peak = 2927.492 ; gain = 872.191
|
|
INFO: [Project 1-571] Translating synthesized netlist
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.224 . Memory (MB): peak = 2927.492 ; gain = 0.000
|
|
INFO: [Netlist 29-17] Analyzing 2769 Unisim elements for replacement
|
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 2927.492 ; gain = 0.000
|
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
|
A total of 27 instances were transformed.
|
|
IOBUF => IOBUF (IBUF, OBUFT): 27 instances
|
|
|
|
Synth Design complete | Checksum: b79aa254
|
|
INFO: [Common 17-83] Releasing license: Synthesis
|
|
223 Infos, 268 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
|
synth_design completed successfully
|
|
synth_design: Time (s): cpu = 00:03:41 ; elapsed = 00:03:45 . Memory (MB): peak = 2927.492 ; gain = 1295.113
|
|
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v10/c64_pro.runs/synth_1/c64pro_top.dcp' has been generated.
|
|
INFO: [runtcl-4] Executing : report_utilization -file c64pro_top_utilization_synth.rpt -pb c64pro_top_utilization_synth.pb
|
|
INFO: [Common 17-206] Exiting Vivado at Fri Sep 4 15:27:46 2026...
|