4912 lines
518 KiB
Plaintext
4912 lines
518 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023
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| Date : Fri Sep 4 15:41:36 2026
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| Host : DESKTOP-VN054CM running 64-bit major release (build 9200)
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| Command : report_timing_summary -max_paths 10 -file c64pro_top_timing_summary_routed.rpt -pb c64pro_top_timing_summary_routed.pb -rpx c64pro_top_timing_summary_routed.rpx -warn_on_violation
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| Design : c64pro_top
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| Device : 7z020-clg400
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| Speed File : -2 PRODUCTION 1.12 2019-11-22
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| Design State : Routed
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-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : No
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Borrow Time for Max Delay Exceptions : Yes
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Merge Timing Exceptions : Yes
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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------------------------------------------------------------------------------------------------
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| Report Methodology
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| ------------------
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------------------------------------------------------------------------------------------------
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Rule Severity Description Violations
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--------- -------- ----------------------------------------------- ----------
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LUTAR-1 Warning LUT drives async reset alert 4
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PDRC-190 Warning Suboptimally placed synchronized register chain 13
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TIMING-18 Warning Missing input or output delay 79
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ULMTCS-1 Warning Control Sets use limits recommend reduction 1
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Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock (0)
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2. checking constant_clock (0)
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3. checking pulse_width_clock (0)
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4. checking unconstrained_internal_endpoints (0)
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5. checking no_input_delay (26)
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6. checking no_output_delay (52)
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7. checking multiple_clock (0)
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8. checking generated_clocks (0)
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9. checking loops (0)
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10. checking partial_input_delay (0)
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11. checking partial_output_delay (0)
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12. checking latch_loops (0)
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1. checking no_clock (0)
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------------------------
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There are 0 register/latch pins with no clock.
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2. checking constant_clock (0)
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------------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock (0)
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---------------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints (0)
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------------------------------------------------
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There are 0 pins that are not constrained for maximum delay.
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay (26)
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-------------------------------
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There are 26 input ports with no input delay specified. (HIGH)
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay (52)
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--------------------------------
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There are 52 ports with no output delay specified. (HIGH)
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There are 0 ports with no output delay but user has a false path constraint
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock (0)
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------------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks (0)
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--------------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops (0)
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---------------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay (0)
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------------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay (0)
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-------------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops (0)
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----------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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0.621 0.000 0 91262 0.036 0.000 0 91246 3.870 0.000 0 36949
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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clk_fpga_0 {0.000 5.000} 10.000 100.000
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dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {0.000 16.500} 33.000 30.303
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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clk_fpga_0 0.621 0.000 0 78371 0.036 0.000 0 78371 3.870 0.000 0 36462
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dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK 27.182 0.000 0 933 0.068 0.000 0 933 15.370 0.000 0 487
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK clk_fpga_0 31.778 0.000 0 8
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clk_fpga_0 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK 8.900 0.000 0 8
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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**async_default** clk_fpga_0 clk_fpga_0 1.288 0.000 0 11842 0.194 0.000 0 11842
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**async_default** dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK 28.554 0.000 0 100 0.361 0.000 0 100
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------------------------------------------------------------------------------------------------
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| Timing Details
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| --------------
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: clk_fpga_0
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To Clock: clk_fpga_0
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Setup : 0 Failing Endpoints, Worst Slack 0.621ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.036ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 3.870ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 0.621ns (required time - arrival time)
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Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[12]/C
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(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shadow_reg[12]/D
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(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: clk_fpga_0
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
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Data Path Delay: 9.138ns (logic 0.538ns (5.888%) route 8.600ns (94.112%))
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Logic Levels: 1 (LUT6=1)
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Clock Path Skew: -0.119ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 2.288ns = ( 12.288 - 10.000 )
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Source Clock Delay (SCD): 2.600ns
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Clock Pessimism Removal (CPR): 0.193ns
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Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.300ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_fpga_0 rise edge)
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0.000 0.000 r
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PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
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net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
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net (fo=36463, routed) 1.521 2.600 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
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SLICE_X102Y37 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[12]/C
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------------------------------------------------------------------- -------------------
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SLICE_X102Y37 FDRE (Prop_fdre_C_Q) 0.433 3.033 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[12]/Q
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net (fo=89, routed) 8.600 11.633 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/s_di_i[12]
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SLICE_X67Y8 LUT6 (Prop_lut6_I1_O) 0.105 11.738 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shadow[12]_i_1/O
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net (fo=1, routed) 0.000 11.738 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shadow[12]
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SLICE_X67Y8 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shadow_reg[12]/D
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------------------------------------------------------------------- -------------------
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(clock clk_fpga_0 rise edge)
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10.000 10.000 r
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PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
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net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
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net (fo=36463, routed) 1.306 12.288 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/s_dclk_i
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SLICE_X67Y8 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shadow_reg[12]/C
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clock pessimism 0.193 12.481
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clock uncertainty -0.154 12.327
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SLICE_X67Y8 FDRE (Setup_fdre_C_D) 0.032 12.359 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[17].mu_srl_reg/shadow_reg[12]
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-------------------------------------------------------------------
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required time 12.359
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arrival time -11.738
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-------------------------------------------------------------------
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slack 0.621
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Slack (MET) : 0.621ns (required time - arrival time)
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Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[0]/C
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(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[0]/D
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(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: clk_fpga_0
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
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Data Path Delay: 9.132ns (logic 0.538ns (5.891%) route 8.594ns (94.109%))
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Logic Levels: 1 (LUT6=1)
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Clock Path Skew: -0.122ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 2.286ns = ( 12.286 - 10.000 )
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Source Clock Delay (SCD): 2.601ns
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Clock Pessimism Removal (CPR): 0.193ns
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Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.300ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_fpga_0 rise edge)
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0.000 0.000 r
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PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
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net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
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net (fo=36463, routed) 1.522 2.601 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
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SLICE_X102Y39 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[0]/C
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------------------------------------------------------------------- -------------------
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SLICE_X102Y39 FDRE (Prop_fdre_C_Q) 0.433 3.034 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[0]/Q
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net (fo=89, routed) 8.594 11.628 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/s_di_i[0]
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SLICE_X67Y12 LUT6 (Prop_lut6_I1_O) 0.105 11.733 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow[0]_i_1/O
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net (fo=1, routed) 0.000 11.733 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow[0]
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SLICE_X67Y12 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[0]/D
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------------------------------------------------------------------- -------------------
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(clock clk_fpga_0 rise edge)
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10.000 10.000 r
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PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
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net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
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net (fo=36463, routed) 1.304 12.286 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/s_dclk_i
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SLICE_X67Y12 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[0]/C
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clock pessimism 0.193 12.479
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clock uncertainty -0.154 12.325
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SLICE_X67Y12 FDRE (Setup_fdre_C_D) 0.030 12.355 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[0]
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-------------------------------------------------------------------
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required time 12.355
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arrival time -11.733
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-------------------------------------------------------------------
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slack 0.621
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Slack (MET) : 0.635ns (required time - arrival time)
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Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
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(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]/D
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(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: clk_fpga_0
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
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Data Path Delay: 9.115ns (logic 0.538ns (5.902%) route 8.577ns (94.098%))
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Logic Levels: 1 (LUT6=1)
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Clock Path Skew: -0.126ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 2.283ns = ( 12.283 - 10.000 )
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Source Clock Delay (SCD): 2.602ns
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Clock Pessimism Removal (CPR): 0.193ns
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Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.300ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock clk_fpga_0 rise edge)
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0.000 0.000 r
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PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
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net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.523 2.602 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X102Y40 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y40 FDRE (Prop_fdre_C_Q) 0.433 3.035 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[14]/Q
|
|
net (fo=89, routed) 8.577 11.612 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/s_di_i[14]
|
|
SLICE_X60Y13 LUT6 (Prop_lut6_I1_O) 0.105 11.717 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow[14]_i_1/O
|
|
net (fo=1, routed) 0.000 11.717 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow[14]
|
|
SLICE_X60Y13 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.301 12.283 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/s_dclk_i
|
|
SLICE_X60Y13 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]/C
|
|
clock pessimism 0.193 12.476
|
|
clock uncertainty -0.154 12.322
|
|
SLICE_X60Y13 FDRE (Setup_fdre_C_D) 0.030 12.352 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[7].mu_srl_reg/shadow_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 12.352
|
|
arrival time -11.717
|
|
-------------------------------------------------------------------
|
|
slack 0.635
|
|
|
|
Slack (MET) : 0.651ns (required time - arrival time)
|
|
Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shadow_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 9.117ns (logic 0.552ns (6.054%) route 8.565ns (93.946%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.122ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.287ns = ( 12.287 - 10.000 )
|
|
Source Clock Delay (SCD): 2.602ns
|
|
Clock Pessimism Removal (CPR): 0.193ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.523 2.602 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X102Y40 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y40 FDRE (Prop_fdre_C_Q) 0.433 3.035 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[15]/Q
|
|
net (fo=89, routed) 8.565 11.600 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/s_di_i[15]
|
|
SLICE_X63Y4 LUT5 (Prop_lut5_I4_O) 0.119 11.719 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shadow[15]_i_1/O
|
|
net (fo=1, routed) 0.000 11.719 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shadow[15]
|
|
SLICE_X63Y4 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shadow_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.305 12.287 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/s_dclk_i
|
|
SLICE_X63Y4 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shadow_reg[15]/C
|
|
clock pessimism 0.193 12.480
|
|
clock uncertainty -0.154 12.326
|
|
SLICE_X63Y4 FDRE (Setup_fdre_C_D) 0.045 12.371 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[8].mu_srl_reg/shadow_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 12.371
|
|
arrival time -11.719
|
|
-------------------------------------------------------------------
|
|
slack 0.651
|
|
|
|
Slack (MET) : 0.679ns (required time - arrival time)
|
|
Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shadow_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 9.079ns (logic 0.484ns (5.331%) route 8.595ns (94.669%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: -0.120ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.287ns = ( 12.287 - 10.000 )
|
|
Source Clock Delay (SCD): 2.600ns
|
|
Clock Pessimism Removal (CPR): 0.193ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.521 2.600 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X99Y38 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X99Y38 FDRE (Prop_fdre_C_Q) 0.379 2.979 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/Q
|
|
net (fo=89, routed) 8.595 11.574 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/s_di_i[10]
|
|
SLICE_X68Y11 LUT6 (Prop_lut6_I1_O) 0.105 11.679 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shadow[10]_i_1/O
|
|
net (fo=1, routed) 0.000 11.679 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shadow[10]
|
|
SLICE_X68Y11 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shadow_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.305 12.287 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/s_dclk_i
|
|
SLICE_X68Y11 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shadow_reg[10]/C
|
|
clock pessimism 0.193 12.480
|
|
clock uncertainty -0.154 12.326
|
|
SLICE_X68Y11 FDRE (Setup_fdre_C_D) 0.032 12.358 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[22].mu_srl_reg/shadow_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 12.358
|
|
arrival time -11.679
|
|
-------------------------------------------------------------------
|
|
slack 0.679
|
|
|
|
Slack (MET) : 0.687ns (required time - arrival time)
|
|
Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shadow_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 9.072ns (logic 0.484ns (5.335%) route 8.588ns (94.665%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.288ns = ( 12.288 - 10.000 )
|
|
Source Clock Delay (SCD): 2.600ns
|
|
Clock Pessimism Removal (CPR): 0.193ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.521 2.600 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X99Y38 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X99Y38 FDRE (Prop_fdre_C_Q) 0.379 2.979 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[10]/Q
|
|
net (fo=89, routed) 8.588 11.567 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/s_di_i[10]
|
|
SLICE_X74Y12 LUT6 (Prop_lut6_I1_O) 0.105 11.672 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shadow[10]_i_1/O
|
|
net (fo=1, routed) 0.000 11.672 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shadow[10]
|
|
SLICE_X74Y12 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shadow_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.306 12.288 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/s_dclk_i
|
|
SLICE_X74Y12 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shadow_reg[10]/C
|
|
clock pessimism 0.193 12.481
|
|
clock uncertainty -0.154 12.327
|
|
SLICE_X74Y12 FDRE (Setup_fdre_C_D) 0.032 12.359 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[19].mu_srl_reg/shadow_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 12.359
|
|
arrival time -11.672
|
|
-------------------------------------------------------------------
|
|
slack 0.687
|
|
|
|
Slack (MET) : 0.725ns (required time - arrival time)
|
|
Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shadow_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 9.034ns (logic 0.538ns (5.955%) route 8.496ns (94.045%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: -0.119ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.289ns = ( 12.289 - 10.000 )
|
|
Source Clock Delay (SCD): 2.601ns
|
|
Clock Pessimism Removal (CPR): 0.193ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.522 2.601 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X102Y39 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y39 FDRE (Prop_fdre_C_Q) 0.433 3.034 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[0]/Q
|
|
net (fo=89, routed) 8.496 11.530 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/s_di_i[0]
|
|
SLICE_X68Y9 LUT6 (Prop_lut6_I1_O) 0.105 11.635 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shadow[0]_i_1/O
|
|
net (fo=1, routed) 0.000 11.635 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shadow[0]
|
|
SLICE_X68Y9 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shadow_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.307 12.289 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/s_dclk_i
|
|
SLICE_X68Y9 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shadow_reg[0]/C
|
|
clock pessimism 0.193 12.482
|
|
clock uncertainty -0.154 12.328
|
|
SLICE_X68Y9 FDRE (Setup_fdre_C_D) 0.032 12.360 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[16].mu_srl_reg/shadow_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 12.360
|
|
arrival time -11.635
|
|
-------------------------------------------------------------------
|
|
slack 0.725
|
|
|
|
Slack (MET) : 0.738ns (required time - arrival time)
|
|
Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shadow_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 9.026ns (logic 0.538ns (5.961%) route 8.488ns (94.039%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: -0.114ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.294ns = ( 12.294 - 10.000 )
|
|
Source Clock Delay (SCD): 2.601ns
|
|
Clock Pessimism Removal (CPR): 0.193ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.522 2.601 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X98Y39 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X98Y39 FDRE (Prop_fdre_C_Q) 0.433 3.034 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[4]/Q
|
|
net (fo=89, routed) 8.488 11.522 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/s_di_i[4]
|
|
SLICE_X84Y5 LUT6 (Prop_lut6_I1_O) 0.105 11.627 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shadow[4]_i_1/O
|
|
net (fo=1, routed) 0.000 11.627 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shadow[4]
|
|
SLICE_X84Y5 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shadow_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.312 12.294 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/s_dclk_i
|
|
SLICE_X84Y5 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shadow_reg[4]/C
|
|
clock pessimism 0.193 12.487
|
|
clock uncertainty -0.154 12.333
|
|
SLICE_X84Y5 FDRE (Setup_fdre_C_D) 0.032 12.365 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[33].mu_srl_reg/shadow_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 12.365
|
|
arrival time -11.627
|
|
-------------------------------------------------------------------
|
|
slack 0.738
|
|
|
|
Slack (MET) : 0.759ns (required time - arrival time)
|
|
Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shadow_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 9.009ns (logic 0.552ns (6.127%) route 8.457ns (93.873%))
|
|
Logic Levels: 1 (LUT5=1)
|
|
Clock Path Skew: -0.122ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.287ns = ( 12.287 - 10.000 )
|
|
Source Clock Delay (SCD): 2.602ns
|
|
Clock Pessimism Removal (CPR): 0.193ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.523 2.602 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X102Y40 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y40 FDRE (Prop_fdre_C_Q) 0.433 3.035 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[15]/Q
|
|
net (fo=89, routed) 8.457 11.492 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/s_di_i[15]
|
|
SLICE_X63Y5 LUT5 (Prop_lut5_I4_O) 0.119 11.611 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shadow[15]_i_1/O
|
|
net (fo=1, routed) 0.000 11.611 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shadow[15]
|
|
SLICE_X63Y5 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shadow_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.305 12.287 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/s_dclk_i
|
|
SLICE_X63Y5 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shadow_reg[15]/C
|
|
clock pessimism 0.193 12.480
|
|
clock uncertainty -0.154 12.326
|
|
SLICE_X63Y5 FDRE (Setup_fdre_C_D) 0.045 12.371 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[11].mu_srl_reg/shadow_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 12.371
|
|
arrival time -11.611
|
|
-------------------------------------------------------------------
|
|
slack 0.759
|
|
|
|
Slack (MET) : 0.767ns (required time - arrival time)
|
|
Source: u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shadow_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.997ns (logic 0.484ns (5.380%) route 8.513ns (94.620%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: -0.114ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.293ns = ( 12.293 - 10.000 )
|
|
Source Clock Delay (SCD): 2.600ns
|
|
Clock Pessimism Removal (CPR): 0.193ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.521 2.600 u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/sl_iport_i[1]
|
|
SLICE_X101Y37 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X101Y37 FDRE (Prop_fdre_C_Q) 0.379 2.979 r u_ila_0/inst/ila_core_inst/u_ila_regs/U_XSDB_SLAVE/G_1PIPE_IFACE.s_di_r_reg[2]/Q
|
|
net (fo=89, routed) 8.513 11.492 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/s_di_i[2]
|
|
SLICE_X79Y3 LUT6 (Prop_lut6_I1_O) 0.105 11.597 r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shadow[2]_i_1/O
|
|
net (fo=1, routed) 0.000 11.597 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shadow[2]
|
|
SLICE_X79Y3 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shadow_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.311 12.293 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/s_dclk_i
|
|
SLICE_X79Y3 FDRE r u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shadow_reg[2]/C
|
|
clock pessimism 0.193 12.486
|
|
clock uncertainty -0.154 12.332
|
|
SLICE_X79Y3 FDRE (Setup_fdre_C_D) 0.032 12.364 u_ila_0/inst/ila_core_inst/u_ila_regs/MU_SRL[3].mu_srl_reg/shadow_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 12.364
|
|
arrival time -11.597
|
|
-------------------------------------------------------------------
|
|
slack 0.767
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.036ns (arrival time - required time)
|
|
Source: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][96]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA/I
|
|
(rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.191ns
|
|
Source Clock Delay (SCD): 0.893ns
|
|
Clock Pessimism Removal (CPR): 0.285ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.557 0.893 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
|
|
SLICE_X37Y52 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][96]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X37Y52 FDRE (Prop_fdre_C_Q) 0.141 1.034 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/switchboards/aw_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][96]/Q
|
|
net (fo=1, routed) 0.055 1.089 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/DIA0
|
|
SLICE_X36Y52 RAMD32 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA/I
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.825 1.191 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/WCLK
|
|
SLICE_X36Y52 RAMD32 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA/CLK
|
|
clock pessimism -0.285 0.906
|
|
SLICE_X36Y52 RAMD32 (Hold_ramd32_CLK_I)
|
|
0.147 1.053 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA
|
|
-------------------------------------------------------------------
|
|
required time -1.053
|
|
arrival time 1.089
|
|
-------------------------------------------------------------------
|
|
slack 0.036
|
|
|
|
Slack (MET) : 0.045ns (arrival time - required time)
|
|
Source: u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_dest_align_reg_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4/D
|
|
(rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.260ns (logic 0.141ns (54.238%) route 0.119ns (45.762%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.032ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.179ns
|
|
Source Clock Delay (SCD): 0.883ns
|
|
Clock Pessimism Removal (CPR): 0.264ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.547 0.883 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk
|
|
SLICE_X40Y79 FDRE r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_dest_align_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X40Y79 FDRE (Prop_fdre_C_Q) 0.141 1.024 r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_dest_align_reg_reg[1]/Q
|
|
net (fo=1, routed) 0.119 1.143 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/in[1]
|
|
SLICE_X38Y79 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.813 1.179 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
|
|
SLICE_X38Y79 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4/CLK
|
|
clock pessimism -0.264 0.915
|
|
SLICE_X38Y79 SRL16E (Hold_srl16e_CLK_D)
|
|
0.183 1.098 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[3][25]_srl4
|
|
-------------------------------------------------------------------
|
|
required time -1.098
|
|
arrival time 1.143
|
|
-------------------------------------------------------------------
|
|
slack 0.045
|
|
|
|
Slack (MET) : 0.051ns (arrival time - required time)
|
|
Source: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state_reg[s_stall_d]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state_reg[s_ready_i]/D
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.396ns (logic 0.186ns (46.982%) route 0.210ns (53.018%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.252ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.210ns
|
|
Source Clock Delay (SCD): 0.928ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.592 0.928 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/aclk
|
|
SLICE_X27Y49 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state_reg[s_stall_d]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X27Y49 FDRE (Prop_fdre_C_Q) 0.141 1.069 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state_reg[s_stall_d]/Q
|
|
net (fo=5, routed) 0.210 1.278 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/p_0_in[0]
|
|
SLICE_X27Y50 LUT6 (Prop_lut6_I5_O) 0.045 1.323 r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state[s_ready_i]_i_1__4/O
|
|
net (fo=1, routed) 0.000 1.323 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state[s_ready_i]_i_1__4_n_0
|
|
SLICE_X27Y50 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state_reg[s_ready_i]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.844 1.210 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/aclk
|
|
SLICE_X27Y50 FDRE r u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state_reg[s_ready_i]/C
|
|
clock pessimism -0.030 1.180
|
|
SLICE_X27Y50 FDRE (Hold_fdre_C_D) 0.092 1.272 u_ps_a9_1/design_a9_1_i/smartconnect_0/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/state_reg[s_ready_i]
|
|
-------------------------------------------------------------------
|
|
required time -1.272
|
|
arrival time 1.323
|
|
-------------------------------------------------------------------
|
|
slack 0.051
|
|
|
|
Slack (MET) : 0.053ns (arrival time - required time)
|
|
Source: u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/storage_data_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][8]_srl16/D
|
|
(rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.251ns (logic 0.141ns (56.078%) route 0.110ns (43.922%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.185ns
|
|
Source Clock Delay (SCD): 0.888ns
|
|
Clock Pessimism Removal (CPR): 0.282ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.552 0.888 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/m_axi_s2mm_aclk
|
|
SLICE_X39Y85 FDRE r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/storage_data_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X39Y85 FDRE (Prop_fdre_C_Q) 0.141 1.029 r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/storage_data_reg[0]/Q
|
|
net (fo=1, routed) 0.110 1.139 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/GEN_INPUT_REG[3].sig_input_data_reg_reg[3][9]_0[0]
|
|
SLICE_X38Y86 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][8]_srl16/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.819 1.185 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk
|
|
SLICE_X38Y86 SRL16E r u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][8]_srl16/CLK
|
|
clock pessimism -0.282 0.903
|
|
SLICE_X38Y86 SRL16E (Hold_srl16e_CLK_D)
|
|
0.183 1.086 u_ps_a9_1/design_a9_1_i/axi_dma_3/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][8]_srl16
|
|
-------------------------------------------------------------------
|
|
required time -1.086
|
|
arrival time 1.139
|
|
-------------------------------------------------------------------
|
|
slack 0.053
|
|
|
|
Slack (MET) : 0.056ns (arrival time - required time)
|
|
Source: u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][290]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2]
|
|
(rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.267ns (logic 0.164ns (61.345%) route 0.103ns (38.655%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.057ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.284ns
|
|
Source Clock Delay (SCD): 0.944ns
|
|
Clock Pessimism Removal (CPR): 0.283ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.608 0.944 u_ila_0/inst/ila_core_inst/DESIGN_CLK_I
|
|
SLICE_X90Y35 FDRE r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][290]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X90Y35 FDRE (Prop_fdre_C_Q) 0.164 1.108 r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][290]/Q
|
|
net (fo=1, routed) 0.103 1.211 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/dina[2]
|
|
RAMB36_X4Y7 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[2]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.918 1.284 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/clka
|
|
RAMB36_X4Y7 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
clock pessimism -0.283 1.000
|
|
RAMB36_X4Y7 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[2])
|
|
0.155 1.155 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[8].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
|
|
-------------------------------------------------------------------
|
|
required time -1.155
|
|
arrival time 1.211
|
|
-------------------------------------------------------------------
|
|
slack 0.056
|
|
|
|
Slack (MET) : 0.057ns (arrival time - required time)
|
|
Source: u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][384]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[22]
|
|
(rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.267ns (logic 0.164ns (61.345%) route 0.103ns (38.655%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.286ns
|
|
Source Clock Delay (SCD): 0.947ns
|
|
Clock Pessimism Removal (CPR): 0.283ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.611 0.947 u_ila_0/inst/ila_core_inst/DESIGN_CLK_I
|
|
SLICE_X90Y41 FDRE r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][384]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X90Y41 FDRE (Prop_fdre_C_Q) 0.164 1.111 r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][384]/Q
|
|
net (fo=1, routed) 0.103 1.214 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/dina[24]
|
|
RAMB36_X4Y8 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[22]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.920 1.286 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/clka
|
|
RAMB36_X4Y8 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
clock pessimism -0.283 1.002
|
|
RAMB36_X4Y8 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[22])
|
|
0.155 1.157 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
|
|
-------------------------------------------------------------------
|
|
required time -1.157
|
|
arrival time 1.214
|
|
-------------------------------------------------------------------
|
|
slack 0.057
|
|
|
|
Slack (MET) : 0.057ns (arrival time - required time)
|
|
Source: u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][329]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.267ns (logic 0.164ns (61.506%) route 0.103ns (38.494%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.055ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.287ns
|
|
Source Clock Delay (SCD): 0.949ns
|
|
Clock Pessimism Removal (CPR): 0.283ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.613 0.949 u_ila_0/inst/ila_core_inst/DESIGN_CLK_I
|
|
SLICE_X90Y47 FDRE r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][329]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X90Y47 FDRE (Prop_fdre_C_Q) 0.164 1.113 r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][329]/Q
|
|
net (fo=1, routed) 0.103 1.215 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/dina[5]
|
|
RAMB36_X4Y9 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.921 1.287 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/clka
|
|
RAMB36_X4Y9 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
clock pessimism -0.283 1.003
|
|
RAMB36_X4Y9 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[5])
|
|
0.155 1.158 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
|
|
-------------------------------------------------------------------
|
|
required time -1.158
|
|
arrival time 1.215
|
|
-------------------------------------------------------------------
|
|
slack 0.057
|
|
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][258]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[6]
|
|
(rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.268ns (logic 0.164ns (61.116%) route 0.104ns (38.884%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.248ns
|
|
Source Clock Delay (SCD): 0.910ns
|
|
Clock Pessimism Removal (CPR): 0.282ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.574 0.910 u_ila_0/inst/ila_core_inst/DESIGN_CLK_I
|
|
SLICE_X54Y30 FDRE r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][258]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X54Y30 FDRE (Prop_fdre_C_Q) 0.164 1.074 r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][258]/Q
|
|
net (fo=1, routed) 0.104 1.178 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/dina[6]
|
|
RAMB36_X3Y6 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[6]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.882 1.248 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/clka
|
|
RAMB36_X3Y6 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
clock pessimism -0.282 0.965
|
|
RAMB36_X3Y6 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[6])
|
|
0.155 1.120 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[7].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
|
|
-------------------------------------------------------------------
|
|
required time -1.120
|
|
arrival time 1.178
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.058ns (arrival time - required time)
|
|
Source: u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][402]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[8]
|
|
(rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.268ns (logic 0.164ns (61.116%) route 0.104ns (38.884%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.056ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.289ns
|
|
Source Clock Delay (SCD): 0.949ns
|
|
Clock Pessimism Removal (CPR): 0.284ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.613 0.949 u_ila_0/inst/ila_core_inst/DESIGN_CLK_I
|
|
SLICE_X104Y41 FDRE r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][402]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X104Y41 FDRE (Prop_fdre_C_Q) 0.164 1.113 r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][402]/Q
|
|
net (fo=1, routed) 0.104 1.217 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/dina[6]
|
|
RAMB36_X5Y8 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[8]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.923 1.289 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/clka
|
|
RAMB36_X5Y8 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
clock pessimism -0.284 1.004
|
|
RAMB36_X5Y8 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[8])
|
|
0.155 1.159 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
|
|
-------------------------------------------------------------------
|
|
required time -1.159
|
|
arrival time 1.217
|
|
-------------------------------------------------------------------
|
|
slack 0.058
|
|
|
|
Slack (MET) : 0.059ns (arrival time - required time)
|
|
Source: u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][113]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[5]
|
|
(rising edge-triggered cell RAMB36E1 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.267ns (logic 0.164ns (61.506%) route 0.103ns (38.494%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.053ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.274ns
|
|
Source Clock Delay (SCD): 0.938ns
|
|
Clock Pessimism Removal (CPR): 0.283ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.602 0.938 u_ila_0/inst/ila_core_inst/DESIGN_CLK_I
|
|
SLICE_X90Y27 FDRE r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][113]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X90Y27 FDRE (Prop_fdre_C_Q) 0.164 1.102 r u_ila_0/inst/ila_core_inst/shifted_data_in_reg[8][113]/Q
|
|
net (fo=1, routed) 0.103 1.204 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/dina[5]
|
|
RAMB36_X4Y5 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/DIADI[5]
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.908 1.274 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/clka
|
|
RAMB36_X4Y5 RAMB36E1 r u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
clock pessimism -0.283 0.990
|
|
RAMB36_X4Y5 RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[5])
|
|
0.155 1.145 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
|
|
-------------------------------------------------------------------
|
|
required time -1.145
|
|
arrival time 1.204
|
|
-------------------------------------------------------------------
|
|
slack 0.059
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: clk_fpga_0
|
|
Waveform(ns): { 0.000 5.000 }
|
|
Period(ns): 10.000
|
|
Sources: { u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X4Y4 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X4Y4 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X4Y8 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X4Y8 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[10].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X5Y8 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X5Y8 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[11].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X3Y4 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X3Y4 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK
|
|
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.472 10.000 7.528 RAMB36_X4Y3 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKARDCLK
|
|
Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.472 10.000 7.528 RAMB36_X4Y3 u_ila_0/inst/ila_core_inst/ila_trace_memory_inst/SUBCORE_RAM_BLK_MEM_1.trace_block_memory/inst_blk_mem_gen/gnbram.gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/prim_noinit.ram/DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram/CLKBWRCLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 5.000 3.870 SLICE_X104Y44 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
To Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 27.182ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.068ns, Total Violation 0.000ns
|
|
PW : 0 Failing Endpoints, Worst Slack 15.370ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 27.182ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 5.793ns (logic 1.432ns (24.720%) route 4.361ns (75.280%))
|
|
Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.023ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.141ns = ( 36.141 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.402ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.379 3.945 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
|
|
net (fo=50, routed) 1.231 5.176 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
|
|
SLICE_X109Y78 LUT4 (Prop_lut4_I1_O) 0.105 5.281 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_7/O
|
|
net (fo=2, routed) 0.850 6.130 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[25]
|
|
SLICE_X110Y78 LUT6 (Prop_lut6_I4_O) 0.105 6.235 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7/O
|
|
net (fo=1, routed) 0.000 6.235 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7_n_0
|
|
SLICE_X110Y78 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.457 6.692 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[3]
|
|
net (fo=4, routed) 1.279 7.972 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
|
|
SLICE_X107Y76 LUT5 (Prop_lut5_I1_O) 0.118 8.090 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
|
|
net (fo=7, routed) 1.001 9.091 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
|
|
SLICE_X106Y76 LUT3 (Prop_lut3_I1_O) 0.268 9.359 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_1/O
|
|
net (fo=1, routed) 0.000 9.359 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_1_n_0
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.401 36.141 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[5]/C
|
|
clock pessimism 0.402 36.543
|
|
clock uncertainty -0.035 36.508
|
|
SLICE_X106Y76 FDRE (Setup_fdre_C_D) 0.033 36.541 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 36.541
|
|
arrival time -9.359
|
|
-------------------------------------------------------------------
|
|
slack 27.182
|
|
|
|
Slack (MET) : 27.324ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 5.650ns (logic 1.432ns (25.346%) route 4.218ns (74.654%))
|
|
Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.023ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.141ns = ( 36.141 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.402ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.379 3.945 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
|
|
net (fo=50, routed) 1.231 5.176 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
|
|
SLICE_X109Y78 LUT4 (Prop_lut4_I1_O) 0.105 5.281 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_7/O
|
|
net (fo=2, routed) 0.850 6.130 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[25]
|
|
SLICE_X110Y78 LUT6 (Prop_lut6_I4_O) 0.105 6.235 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7/O
|
|
net (fo=1, routed) 0.000 6.235 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7_n_0
|
|
SLICE_X110Y78 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.457 6.692 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[3]
|
|
net (fo=4, routed) 1.279 7.972 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
|
|
SLICE_X107Y76 LUT5 (Prop_lut5_I1_O) 0.118 8.090 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
|
|
net (fo=7, routed) 0.858 8.948 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
|
|
SLICE_X106Y76 LUT3 (Prop_lut3_I1_O) 0.268 9.216 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[4]_i_1/O
|
|
net (fo=1, routed) 0.000 9.216 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[4]_i_1_n_0
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.401 36.141 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[4]/C
|
|
clock pessimism 0.402 36.543
|
|
clock uncertainty -0.035 36.508
|
|
SLICE_X106Y76 FDRE (Setup_fdre_C_D) 0.032 36.540 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 36.540
|
|
arrival time -9.216
|
|
-------------------------------------------------------------------
|
|
slack 27.324
|
|
|
|
Slack (MET) : 27.611ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 5.362ns (logic 1.432ns (26.704%) route 3.930ns (73.296%))
|
|
Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.143ns = ( 36.143 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.402ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.379 3.945 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
|
|
net (fo=50, routed) 1.231 5.176 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
|
|
SLICE_X109Y78 LUT4 (Prop_lut4_I1_O) 0.105 5.281 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_7/O
|
|
net (fo=2, routed) 0.850 6.130 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[25]
|
|
SLICE_X110Y78 LUT6 (Prop_lut6_I4_O) 0.105 6.235 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7/O
|
|
net (fo=1, routed) 0.000 6.235 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7_n_0
|
|
SLICE_X110Y78 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.457 6.692 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[3]
|
|
net (fo=4, routed) 1.279 7.972 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
|
|
SLICE_X107Y76 LUT5 (Prop_lut5_I1_O) 0.118 8.090 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
|
|
net (fo=7, routed) 0.571 8.660 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
|
|
SLICE_X106Y77 LUT3 (Prop_lut3_I1_O) 0.268 8.928 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[2]_i_1/O
|
|
net (fo=1, routed) 0.000 8.928 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[2]_i_1_n_0
|
|
SLICE_X106Y77 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.403 36.143 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X106Y77 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[2]/C
|
|
clock pessimism 0.402 36.545
|
|
clock uncertainty -0.035 36.510
|
|
SLICE_X106Y77 FDRE (Setup_fdre_C_D) 0.030 36.540 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 36.540
|
|
arrival time -8.928
|
|
-------------------------------------------------------------------
|
|
slack 27.611
|
|
|
|
Slack (MET) : 27.616ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[0]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 5.359ns (logic 1.432ns (26.720%) route 3.927ns (73.280%))
|
|
Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.143ns = ( 36.143 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.402ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.379 3.945 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
|
|
net (fo=50, routed) 1.231 5.176 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
|
|
SLICE_X109Y78 LUT4 (Prop_lut4_I1_O) 0.105 5.281 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_7/O
|
|
net (fo=2, routed) 0.850 6.130 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[25]
|
|
SLICE_X110Y78 LUT6 (Prop_lut6_I4_O) 0.105 6.235 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7/O
|
|
net (fo=1, routed) 0.000 6.235 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7_n_0
|
|
SLICE_X110Y78 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.457 6.692 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[3]
|
|
net (fo=4, routed) 1.279 7.972 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
|
|
SLICE_X107Y76 LUT5 (Prop_lut5_I1_O) 0.118 8.090 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
|
|
net (fo=7, routed) 0.568 8.657 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
|
|
SLICE_X106Y77 LUT3 (Prop_lut3_I1_O) 0.268 8.925 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[0]_i_1/O
|
|
net (fo=1, routed) 0.000 8.925 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[0]_i_1_n_0
|
|
SLICE_X106Y77 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.403 36.143 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X106Y77 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[0]/C
|
|
clock pessimism 0.402 36.545
|
|
clock uncertainty -0.035 36.510
|
|
SLICE_X106Y77 FDRE (Setup_fdre_C_D) 0.032 36.542 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 36.542
|
|
arrival time -8.925
|
|
-------------------------------------------------------------------
|
|
slack 27.616
|
|
|
|
Slack (MET) : 27.616ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 5.359ns (logic 1.432ns (26.720%) route 3.927ns (73.280%))
|
|
Logic Levels: 5 (CARRY4=1 LUT4=1 LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.021ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.143ns = ( 36.143 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.402ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.379 3.945 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
|
|
net (fo=50, routed) 1.231 5.176 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
|
|
SLICE_X109Y78 LUT4 (Prop_lut4_I1_O) 0.105 5.281 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_7/O
|
|
net (fo=2, routed) 0.850 6.130 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[25]
|
|
SLICE_X110Y78 LUT6 (Prop_lut6_I4_O) 0.105 6.235 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7/O
|
|
net (fo=1, routed) 0.000 6.235 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7_n_0
|
|
SLICE_X110Y78 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.457 6.692 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[3]
|
|
net (fo=4, routed) 1.279 7.972 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
|
|
SLICE_X107Y76 LUT5 (Prop_lut5_I1_O) 0.118 8.090 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
|
|
net (fo=7, routed) 0.568 8.657 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
|
|
SLICE_X107Y77 LUT6 (Prop_lut6_I2_O) 0.268 8.925 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_1/O
|
|
net (fo=1, routed) 0.000 8.925 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[2]_i_1_n_0
|
|
SLICE_X107Y77 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.403 36.143 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y77 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]/C
|
|
clock pessimism 0.402 36.545
|
|
clock uncertainty -0.035 36.510
|
|
SLICE_X107Y77 FDRE (Setup_fdre_C_D) 0.032 36.542 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 36.542
|
|
arrival time -8.925
|
|
-------------------------------------------------------------------
|
|
slack 27.616
|
|
|
|
Slack (MET) : 27.736ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 5.235ns (logic 1.432ns (27.352%) route 3.803ns (72.648%))
|
|
Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.023ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.141ns = ( 36.141 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.402ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.379 3.945 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
|
|
net (fo=50, routed) 1.231 5.176 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
|
|
SLICE_X109Y78 LUT4 (Prop_lut4_I1_O) 0.105 5.281 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_7/O
|
|
net (fo=2, routed) 0.850 6.130 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[25]
|
|
SLICE_X110Y78 LUT6 (Prop_lut6_I4_O) 0.105 6.235 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7/O
|
|
net (fo=1, routed) 0.000 6.235 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7_n_0
|
|
SLICE_X110Y78 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.457 6.692 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[3]
|
|
net (fo=4, routed) 1.279 7.972 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
|
|
SLICE_X107Y76 LUT5 (Prop_lut5_I1_O) 0.118 8.090 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
|
|
net (fo=7, routed) 0.444 8.533 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
|
|
SLICE_X106Y76 LUT3 (Prop_lut3_I1_O) 0.268 8.801 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[1]_i_1/O
|
|
net (fo=1, routed) 0.000 8.801 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[1]_i_1_n_0
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.401 36.141 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[1]/C
|
|
clock pessimism 0.402 36.543
|
|
clock uncertainty -0.035 36.508
|
|
SLICE_X106Y76 FDRE (Setup_fdre_C_D) 0.030 36.538 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 36.538
|
|
arrival time -8.801
|
|
-------------------------------------------------------------------
|
|
slack 27.736
|
|
|
|
Slack (MET) : 27.741ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 5.232ns (logic 1.432ns (27.369%) route 3.800ns (72.631%))
|
|
Logic Levels: 5 (CARRY4=1 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.023ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.141ns = ( 36.141 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.402ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.379 3.945 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
|
|
net (fo=50, routed) 1.231 5.176 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
|
|
SLICE_X109Y78 LUT4 (Prop_lut4_I1_O) 0.105 5.281 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid_inferred_i_7/O
|
|
net (fo=2, routed) 0.850 6.130 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/curid[25]
|
|
SLICE_X110Y78 LUT6 (Prop_lut6_I4_O) 0.105 6.235 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7/O
|
|
net (fo=1, routed) 0.000 6.235 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp[0]_i_7_n_0
|
|
SLICE_X110Y78 CARRY4 (Prop_carry4_S[1]_CO[3])
|
|
0.457 6.692 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3/CO[3]
|
|
net (fo=4, routed) 1.279 7.972 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_temp_reg[0]_i_3_n_0
|
|
SLICE_X107Y76 LUT5 (Prop_lut5_I1_O) 0.118 8.090 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2/O
|
|
net (fo=7, routed) 0.441 8.530 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[5]_i_2_n_0
|
|
SLICE_X106Y76 LUT3 (Prop_lut3_I1_O) 0.268 8.798 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[3]_i_1/O
|
|
net (fo=1, routed) 0.000 8.798 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp[3]_i_1_n_0
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.401 36.141 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X106Y76 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]/C
|
|
clock pessimism 0.402 36.543
|
|
clock uncertainty -0.035 36.508
|
|
SLICE_X106Y76 FDRE (Setup_fdre_C_D) 0.032 36.540 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_temp_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 36.540
|
|
arrival time -8.798
|
|
-------------------------------------------------------------------
|
|
slack 27.741
|
|
|
|
Slack (MET) : 28.137ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.361ns (logic 0.905ns (20.754%) route 3.456ns (79.246%))
|
|
Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.526 5.314 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT5 (Prop_lut5_I3_O) 0.105 5.419 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
|
|
net (fo=4, routed) 1.379 6.798 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
|
|
SLICE_X112Y58 LUT4 (Prop_lut4_I1_O) 0.105 6.903 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
|
|
net (fo=1, routed) 0.516 7.419 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
|
|
SLICE_X111Y59 LUT5 (Prop_lut5_I4_O) 0.105 7.524 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
|
|
net (fo=6, routed) 0.403 7.927 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
|
|
SLICE_X112Y59 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
|
|
SLICE_X112Y59 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X112Y59 FDRE (Setup_fdre_C_R) -0.423 36.064 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 36.064
|
|
arrival time -7.927
|
|
-------------------------------------------------------------------
|
|
slack 28.137
|
|
|
|
Slack (MET) : 28.137ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.361ns (logic 0.905ns (20.754%) route 3.456ns (79.246%))
|
|
Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.526 5.314 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT5 (Prop_lut5_I3_O) 0.105 5.419 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
|
|
net (fo=4, routed) 1.379 6.798 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
|
|
SLICE_X112Y58 LUT4 (Prop_lut4_I1_O) 0.105 6.903 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
|
|
net (fo=1, routed) 0.516 7.419 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
|
|
SLICE_X111Y59 LUT5 (Prop_lut5_I4_O) 0.105 7.524 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
|
|
net (fo=6, routed) 0.403 7.927 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
|
|
SLICE_X112Y59 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
|
|
SLICE_X112Y59 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X112Y59 FDRE (Setup_fdre_C_R) -0.423 36.064 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 36.064
|
|
arrival time -7.927
|
|
-------------------------------------------------------------------
|
|
slack 28.137
|
|
|
|
Slack (MET) : 28.137ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.361ns (logic 0.905ns (20.754%) route 3.456ns (79.246%))
|
|
Logic Levels: 4 (LUT4=1 LUT5=2 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.526 5.314 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT5 (Prop_lut5_I3_O) 0.105 5.419 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_shift[0]_INST_0/O
|
|
net (fo=4, routed) 1.379 6.798 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/icn_cmd_en_reg[7]
|
|
SLICE_X112Y58 LUT4 (Prop_lut4_I1_O) 0.105 6.903 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4/O
|
|
net (fo=1, routed) 0.516 7.419 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_4_n_0
|
|
SLICE_X111Y59 LUT5 (Prop_lut5_I4_O) 0.105 7.524 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSTAT_CNT[5]_i_1/O
|
|
net (fo=6, routed) 0.403 7.927 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/SR[0]
|
|
SLICE_X112Y59 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/R
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
|
|
SLICE_X112Y59 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X112Y59 FDRE (Setup_fdre_C_R) -0.423 36.064 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 36.064
|
|
arrival time -7.927
|
|
-------------------------------------------------------------------
|
|
slack 28.137
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC_D1/WADR1
|
|
(rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC_D1/WADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC_D1/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMD32 (Hold_ramd32_CLK_WADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC_D1
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMS32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMS32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.068ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD_D1/ADR1
|
|
(rising edge-triggered cell RAMS32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.414ns (logic 0.141ns (34.049%) route 0.273ns (65.951%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X103Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y51 FDCE (Prop_fdce_C_Q) 0.141 1.776 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/Q
|
|
net (fo=26, routed) 0.273 2.049 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/ADDRD1
|
|
SLICE_X104Y52 RAMS32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD_D1/ADR1
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/WCLK
|
|
SLICE_X104Y52 RAMS32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD_D1/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y52 RAMS32 (Hold_rams32_CLK_ADR1)
|
|
0.309 1.981 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMD_D1
|
|
-------------------------------------------------------------------
|
|
required time -1.981
|
|
arrival time 2.049
|
|
-------------------------------------------------------------------
|
|
slack 0.068
|
|
|
|
Slack (MET) : 0.086ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[19]/D
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.349ns (logic 0.128ns (36.686%) route 0.221ns (63.314%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.270ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.070ns
|
|
Source Clock Delay (SCD): 1.665ns
|
|
Clock Pessimism Removal (CPR): 0.135ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.641 1.665 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
|
|
SLICE_X110Y49 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X110Y49 FDRE (Prop_fdre_C_Q) 0.128 1.793 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/Q
|
|
net (fo=2, routed) 0.221 2.013 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[20]
|
|
SLICE_X110Y50 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.911 2.070 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
|
|
SLICE_X110Y50 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[19]/C
|
|
clock pessimism -0.135 1.935
|
|
SLICE_X110Y50 FDRE (Hold_fdre_C_D) -0.007 1.928 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time -1.928
|
|
arrival time 2.013
|
|
-------------------------------------------------------------------
|
|
slack 0.086
|
|
|
|
Slack (MET) : 0.091ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_6_11/RAMA/WADR2
|
|
(rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.382ns (logic 0.164ns (42.942%) route 0.218ns (57.058%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.037ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.041ns
|
|
Source Clock Delay (SCD): 1.635ns
|
|
Clock Pessimism Removal (CPR): 0.369ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.611 1.635 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
|
|
SLICE_X102Y51 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y51 FDCE (Prop_fdce_C_Q) 0.164 1.799 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[2]/Q
|
|
net (fo=26, routed) 0.218 2.017 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_6_11/ADDRD2
|
|
SLICE_X104Y50 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_6_11/RAMA/WADR2
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.882 2.041 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_6_11/WCLK
|
|
SLICE_X104Y50 RAMD32 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_6_11/RAMA/CLK
|
|
clock pessimism -0.369 1.672
|
|
SLICE_X104Y50 RAMD32 (Hold_ramd32_CLK_WADR2)
|
|
0.254 1.926 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_6_11/RAMA
|
|
-------------------------------------------------------------------
|
|
required time -1.926
|
|
arrival time 2.017
|
|
-------------------------------------------------------------------
|
|
slack 0.091
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Waveform(ns): { 0.000 16.500 }
|
|
Period(ns): 33.000
|
|
Sources: { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 1.592 33.000 31.408 BUFGCTRL_X0Y0 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X111Y80 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X111Y82 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X111Y82 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[11]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X112Y82 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[12]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X112Y82 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[13]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X112Y83 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[14]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X112Y83 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[15]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X111Y83 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[16]/C
|
|
Min Period n/a FDRE/C n/a 1.000 33.000 32.000 SLICE_X111Y83 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[17]/C
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
Low Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
Low Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMA_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMB_D1/CLK
|
|
High Pulse Width Slow RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
High Pulse Width Fast RAMD32/CLK n/a 1.130 16.500 15.370 SLICE_X104Y52 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_5/RAMC/CLK
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
To Clock: clk_fpga_0
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 31.778ns, Total Violation 0.000ns
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 31.778ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 1.015ns (logic 0.348ns (34.271%) route 0.667ns (65.729%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y52 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
|
|
SLICE_X103Y52 FDCE (Prop_fdce_C_Q) 0.348 0.348 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
|
|
net (fo=1, routed) 0.667 1.015 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
|
|
SLICE_X103Y50 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X103Y50 FDCE (Setup_fdce_C_D) -0.207 32.793 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 32.793
|
|
arrival time -1.015
|
|
-------------------------------------------------------------------
|
|
slack 31.778
|
|
|
|
Slack (MET) : 31.889ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 0.908ns (logic 0.398ns (43.841%) route 0.510ns (56.159%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y42 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
|
|
SLICE_X112Y42 FDCE (Prop_fdce_C_Q) 0.398 0.398 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
|
|
net (fo=1, routed) 0.510 0.908 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
|
|
SLICE_X111Y42 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X111Y42 FDCE (Setup_fdce_C_D) -0.203 32.797 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 32.797
|
|
arrival time -0.908
|
|
-------------------------------------------------------------------
|
|
slack 31.889
|
|
|
|
Slack (MET) : 32.008ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 0.963ns (logic 0.433ns (44.982%) route 0.530ns (55.018%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y42 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
|
|
SLICE_X112Y42 FDCE (Prop_fdce_C_Q) 0.433 0.433 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
|
|
net (fo=1, routed) 0.530 0.963 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
|
|
SLICE_X112Y43 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X112Y43 FDCE (Setup_fdce_C_D) -0.029 32.971 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 32.971
|
|
arrival time -0.963
|
|
-------------------------------------------------------------------
|
|
slack 32.008
|
|
|
|
Slack (MET) : 32.015ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 0.952ns (logic 0.433ns (45.491%) route 0.519ns (54.509%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y42 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
|
SLICE_X112Y42 FDCE (Prop_fdce_C_Q) 0.433 0.433 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
|
|
net (fo=1, routed) 0.519 0.952 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
|
|
SLICE_X112Y43 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X112Y43 FDCE (Setup_fdce_C_D) -0.033 32.967 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 32.967
|
|
arrival time -0.952
|
|
-------------------------------------------------------------------
|
|
slack 32.015
|
|
|
|
Slack (MET) : 32.101ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 0.743ns (logic 0.398ns (53.550%) route 0.345ns (46.450%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y52 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
|
|
SLICE_X102Y52 FDCE (Prop_fdce_C_Q) 0.398 0.398 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
|
|
net (fo=1, routed) 0.345 0.743 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
|
|
SLICE_X102Y50 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X102Y50 FDCE (Setup_fdce_C_D) -0.156 32.844 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 32.844
|
|
arrival time -0.743
|
|
-------------------------------------------------------------------
|
|
slack 32.101
|
|
|
|
Slack (MET) : 32.190ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 0.777ns (logic 0.433ns (55.697%) route 0.344ns (44.303%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y52 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
|
|
SLICE_X102Y52 FDCE (Prop_fdce_C_Q) 0.433 0.433 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
|
|
net (fo=1, routed) 0.344 0.777 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
|
|
SLICE_X102Y50 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X102Y50 FDCE (Setup_fdce_C_D) -0.033 32.967 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 32.967
|
|
arrival time -0.777
|
|
-------------------------------------------------------------------
|
|
slack 32.190
|
|
|
|
Slack (MET) : 32.205ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 0.720ns (logic 0.379ns (52.608%) route 0.341ns (47.392%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X103Y52 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
|
SLICE_X103Y52 FDCE (Prop_fdce_C_Q) 0.379 0.379 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
|
|
net (fo=1, routed) 0.341 0.720 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
|
|
SLICE_X103Y50 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X103Y50 FDCE (Setup_fdce_C_D) -0.075 32.925 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 32.925
|
|
arrival time -0.720
|
|
-------------------------------------------------------------------
|
|
slack 32.205
|
|
|
|
Slack (MET) : 32.210ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: clk_fpga_0
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (MaxDelay Path 33.000ns)
|
|
Data Path Delay: 0.715ns (logic 0.379ns (52.994%) route 0.336ns (47.006%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 33.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X110Y41 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
|
SLICE_X110Y41 FDCE (Prop_fdce_C_Q) 0.379 0.379 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
|
|
net (fo=1, routed) 0.336 0.715 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
|
|
SLICE_X111Y42 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 33.000 33.000
|
|
SLICE_X111Y42 FDCE (Setup_fdce_C_D) -0.075 32.925 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 32.925
|
|
arrival time -0.715
|
|
-------------------------------------------------------------------
|
|
slack 32.210
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
From Clock: clk_fpga_0
|
|
To Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 8.900ns, Total Violation 0.000ns
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 8.900ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 1.021ns (logic 0.379ns (37.133%) route 0.642ns (62.867%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X105Y50 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
|
|
SLICE_X105Y50 FDCE (Prop_fdce_C_Q) 0.379 0.379 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
|
|
net (fo=1, routed) 0.642 1.021 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
|
|
SLICE_X103Y52 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X103Y52 FDCE (Setup_fdce_C_D) -0.079 9.921 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 9.921
|
|
arrival time -1.021
|
|
-------------------------------------------------------------------
|
|
slack 8.900
|
|
|
|
Slack (MET) : 8.985ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 0.807ns (logic 0.348ns (43.145%) route 0.459ns (56.855%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X111Y42 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
|
|
SLICE_X111Y42 FDCE (Prop_fdce_C_Q) 0.348 0.348 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
|
|
net (fo=1, routed) 0.459 0.807 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X111Y41 FDCE (Setup_fdce_C_D) -0.208 9.792 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 9.792
|
|
arrival time -0.807
|
|
-------------------------------------------------------------------
|
|
slack 8.985
|
|
|
|
Slack (MET) : 9.039ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 0.749ns (logic 0.348ns (46.485%) route 0.401ns (53.515%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X105Y50 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
|
SLICE_X105Y50 FDCE (Prop_fdce_C_Q) 0.348 0.348 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
|
|
net (fo=1, routed) 0.401 0.749 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
|
|
SLICE_X105Y52 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X105Y52 FDCE (Setup_fdce_C_D) -0.212 9.788 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 9.788
|
|
arrival time -0.749
|
|
-------------------------------------------------------------------
|
|
slack 9.039
|
|
|
|
Slack (MET) : 9.081ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 0.759ns (logic 0.398ns (52.467%) route 0.361ns (47.533%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y43 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
|
|
SLICE_X112Y43 FDCE (Prop_fdce_C_Q) 0.398 0.398 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
|
|
net (fo=1, routed) 0.361 0.759 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
|
|
SLICE_X112Y42 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X112Y42 FDCE (Setup_fdce_C_D) -0.160 9.840 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 9.840
|
|
arrival time -0.759
|
|
-------------------------------------------------------------------
|
|
slack 9.081
|
|
|
|
Slack (MET) : 9.084ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 0.709ns (logic 0.348ns (49.062%) route 0.361ns (50.938%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X105Y50 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
|
|
SLICE_X105Y50 FDCE (Prop_fdce_C_Q) 0.348 0.348 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
|
|
net (fo=1, routed) 0.361 0.709 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
|
|
SLICE_X105Y52 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X105Y52 FDCE (Setup_fdce_C_D) -0.207 9.793 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 9.793
|
|
arrival time -0.709
|
|
-------------------------------------------------------------------
|
|
slack 9.084
|
|
|
|
Slack (MET) : 9.186ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 0.781ns (logic 0.433ns (55.412%) route 0.348ns (44.588%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X102Y50 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
|
|
SLICE_X102Y50 FDCE (Prop_fdce_C_Q) 0.433 0.433 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
|
|
net (fo=1, routed) 0.348 0.781 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
|
|
SLICE_X102Y52 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X102Y52 FDCE (Setup_fdce_C_D) -0.033 9.967 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 9.967
|
|
arrival time -0.781
|
|
-------------------------------------------------------------------
|
|
slack 9.186
|
|
|
|
Slack (MET) : 9.199ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 0.726ns (logic 0.379ns (52.222%) route 0.347ns (47.778%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X111Y42 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
|
|
SLICE_X111Y42 FDCE (Prop_fdce_C_Q) 0.379 0.379 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
|
|
net (fo=1, routed) 0.347 0.726 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X111Y41 FDCE (Setup_fdce_C_D) -0.075 9.925 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 9.925
|
|
arrival time -0.726
|
|
-------------------------------------------------------------------
|
|
slack 9.199
|
|
|
|
Slack (MET) : 9.203ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (MaxDelay Path 10.000ns)
|
|
Data Path Delay: 0.722ns (logic 0.379ns (52.460%) route 0.343ns (47.540%))
|
|
Logic Levels: 0
|
|
Timing Exception: MaxDelay Path 10.000ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X111Y43 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
|
|
SLICE_X111Y43 FDCE (Prop_fdce_C_Q) 0.379 0.379 r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
|
|
net (fo=1, routed) 0.343 0.722 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
|
|
SLICE_X110Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 10.000 10.000
|
|
SLICE_X110Y41 FDCE (Setup_fdce_C_D) -0.075 9.925 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 9.925
|
|
arrival time -0.722
|
|
-------------------------------------------------------------------
|
|
slack 9.203
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: clk_fpga_0
|
|
To Clock: clk_fpga_0
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 1.288ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.194ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 1.288ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[4]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.193ns (logic 0.484ns (5.907%) route 7.709ns (94.093%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.034ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.398ns = ( 12.398 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.378 10.721 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X113Y93 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.415 12.398 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X113Y93 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[4]/C
|
|
clock pessimism 0.097 12.494
|
|
clock uncertainty -0.154 12.340
|
|
SLICE_X113Y93 FDCE (Recov_fdce_C_CLR) -0.331 12.009 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 12.009
|
|
arrival time -10.721
|
|
-------------------------------------------------------------------
|
|
slack 1.288
|
|
|
|
Slack (MET) : 1.288ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[5]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.193ns (logic 0.484ns (5.907%) route 7.709ns (94.093%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.034ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.398ns = ( 12.398 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.378 10.721 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X113Y93 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.415 12.398 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X113Y93 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[5]/C
|
|
clock pessimism 0.097 12.494
|
|
clock uncertainty -0.154 12.340
|
|
SLICE_X113Y93 FDCE (Recov_fdce_C_CLR) -0.331 12.009 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 12.009
|
|
arrival time -10.721
|
|
-------------------------------------------------------------------
|
|
slack 1.288
|
|
|
|
Slack (MET) : 1.288ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[6]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.193ns (logic 0.484ns (5.907%) route 7.709ns (94.093%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.034ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.398ns = ( 12.398 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.378 10.721 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X113Y93 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.415 12.398 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X113Y93 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[6]/C
|
|
clock pessimism 0.097 12.494
|
|
clock uncertainty -0.154 12.340
|
|
SLICE_X113Y93 FDCE (Recov_fdce_C_CLR) -0.331 12.009 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 12.009
|
|
arrival time -10.721
|
|
-------------------------------------------------------------------
|
|
slack 1.288
|
|
|
|
Slack (MET) : 1.288ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[7]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.193ns (logic 0.484ns (5.907%) route 7.709ns (94.093%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.034ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.398ns = ( 12.398 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.378 10.721 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X113Y93 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.415 12.398 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X113Y93 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[7]/C
|
|
clock pessimism 0.097 12.494
|
|
clock uncertainty -0.154 12.340
|
|
SLICE_X113Y93 FDCE (Recov_fdce_C_CLR) -0.331 12.009 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 12.009
|
|
arrival time -10.721
|
|
-------------------------------------------------------------------
|
|
slack 1.288
|
|
|
|
Slack (MET) : 1.298ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[0]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.181ns (logic 0.484ns (5.916%) route 7.697ns (94.084%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.396ns = ( 12.396 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.366 10.709 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X109Y93 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.413 12.396 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X109Y93 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[0]/C
|
|
clock pessimism 0.097 12.492
|
|
clock uncertainty -0.154 12.338
|
|
SLICE_X109Y93 FDCE (Recov_fdce_C_CLR) -0.331 12.007 u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 12.007
|
|
arrival time -10.709
|
|
-------------------------------------------------------------------
|
|
slack 1.298
|
|
|
|
Slack (MET) : 1.298ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[5]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.181ns (logic 0.484ns (5.916%) route 7.697ns (94.084%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.396ns = ( 12.396 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.366 10.709 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X109Y93 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.413 12.396 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X109Y93 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[5]/C
|
|
clock pessimism 0.097 12.492
|
|
clock uncertainty -0.154 12.338
|
|
SLICE_X109Y93 FDCE (Recov_fdce_C_CLR) -0.331 12.007 u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 12.007
|
|
arrival time -10.709
|
|
-------------------------------------------------------------------
|
|
slack 1.298
|
|
|
|
Slack (MET) : 1.337ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[2]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.181ns (logic 0.484ns (5.916%) route 7.697ns (94.084%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.396ns = ( 12.396 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.366 10.709 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X108Y93 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.413 12.396 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X108Y93 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[2]/C
|
|
clock pessimism 0.097 12.492
|
|
clock uncertainty -0.154 12.338
|
|
SLICE_X108Y93 FDCE (Recov_fdce_C_CLR) -0.292 12.046 u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 12.046
|
|
arrival time -10.709
|
|
-------------------------------------------------------------------
|
|
slack 1.337
|
|
|
|
Slack (MET) : 1.339ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[2]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.073ns (logic 0.484ns (5.995%) route 7.589ns (94.005%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.103ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.329ns = ( 12.329 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.258 10.601 u_pl_top/u0_upload_top/u_upload_protocol_ql/m_axis_record_tdata_reg[0]_0
|
|
SLICE_X95Y94 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.346 12.329 u_pl_top/u0_upload_top/u_upload_protocol_ql/clk
|
|
SLICE_X95Y94 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[2]/C
|
|
clock pessimism 0.097 12.425
|
|
clock uncertainty -0.154 12.271
|
|
SLICE_X95Y94 FDCE (Recov_fdce_C_CLR) -0.331 11.940 u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 11.940
|
|
arrival time -10.601
|
|
-------------------------------------------------------------------
|
|
slack 1.339
|
|
|
|
Slack (MET) : 1.339ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[5]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.073ns (logic 0.484ns (5.995%) route 7.589ns (94.005%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.103ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.329ns = ( 12.329 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.258 10.601 u_pl_top/u0_upload_top/u_upload_protocol_ql/m_axis_record_tdata_reg[0]_0
|
|
SLICE_X95Y94 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.346 12.329 u_pl_top/u0_upload_top/u_upload_protocol_ql/clk
|
|
SLICE_X95Y94 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[5]/C
|
|
clock pessimism 0.097 12.425
|
|
clock uncertainty -0.154 12.271
|
|
SLICE_X95Y94 FDCE (Recov_fdce_C_CLR) -0.331 11.940 u_pl_top/u0_upload_top/u_upload_protocol_ql/byte_cnt_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 11.940
|
|
arrival time -10.601
|
|
-------------------------------------------------------------------
|
|
slack 1.339
|
|
|
|
Slack (MET) : 1.340ns (required time - arrival time)
|
|
Source: u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[6]/CLR
|
|
(recovery check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 8.211ns (logic 0.484ns (5.895%) route 7.727ns (94.106%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.037ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 2.395ns = ( 12.395 - 10.000 )
|
|
Source Clock Delay (SCD): 2.528ns
|
|
Clock Pessimism Removal (CPR): 0.097ns
|
|
Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.300ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.994 0.994 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.085 1.079 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.449 2.528 u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/slowest_sync_clk
|
|
SLICE_X74Y27 FDRE r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X74Y27 FDRE (Prop_fdre_C_Q) 0.379 2.907 r u_ps_a9_1/design_a9_1_i/rst_ps7_0_50M/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
|
|
net (fo=109, routed) 4.331 7.238 u_pl_top/u0_upload_top/u_upload_sort/rst_n
|
|
SLICE_X31Y134 LUT1 (Prop_lut1_I0_O) 0.105 7.343 f u_pl_top/u0_upload_top/u_upload_sort/bram_dout[31]_i_3/O
|
|
net (fo=4445, routed) 3.396 10.739 u_pl_top/u0_upload_top/u_upload_protocol_intan/package_id_reg[0]_0
|
|
SLICE_X108Y91 FDCE f u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
10.000 10.000 r
|
|
PS7_X0Y0 PS7 0.000 10.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.905 10.906 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 10.983 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 1.412 12.395 u_pl_top/u0_upload_top/u_upload_protocol_intan/clk
|
|
SLICE_X108Y91 FDCE r u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[6]/C
|
|
clock pessimism 0.097 12.491
|
|
clock uncertainty -0.154 12.337
|
|
SLICE_X108Y91 FDCE (Recov_fdce_C_CLR) -0.258 12.079 u_pl_top/u0_upload_top/u_upload_protocol_intan/FSM_onehot_cstate_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 12.079
|
|
arrival time -10.739
|
|
-------------------------------------------------------------------
|
|
slack 1.340
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.194ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
|
|
(rising edge-triggered cell FDPE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.347ns (logic 0.128ns (36.924%) route 0.219ns (63.076%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.279ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X107Y51 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y51 FDPE (Prop_fdpe_C_Q) 0.128 1.100 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/Q
|
|
net (fo=1, routed) 0.219 1.318 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2
|
|
SLICE_X108Y49 FDPE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.913 1.279 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X108Y49 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/C
|
|
clock pessimism -0.030 1.249
|
|
SLICE_X108Y49 FDPE (Remov_fdpe_C_PRE) -0.125 1.124 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.124
|
|
arrival time 1.318
|
|
-------------------------------------------------------------------
|
|
slack 0.194
|
|
|
|
Slack (MET) : 0.243ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.428ns (logic 0.141ns (32.917%) route 0.287ns (67.083%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.279ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.287 1.400 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X109Y49 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.913 1.279 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X109Y49 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/C
|
|
clock pessimism -0.030 1.249
|
|
SLICE_X109Y49 FDCE (Remov_fdce_C_CLR) -0.092 1.157 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.157
|
|
arrival time 1.400
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.243ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[1]/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.428ns (logic 0.141ns (32.917%) route 0.287ns (67.083%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.279ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.287 1.400 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X109Y49 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.913 1.279 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X109Y49 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[1]/C
|
|
clock pessimism -0.030 1.249
|
|
SLICE_X109Y49 FDCE (Remov_fdce_C_CLR) -0.092 1.157 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.157
|
|
arrival time 1.400
|
|
-------------------------------------------------------------------
|
|
slack 0.243
|
|
|
|
Slack (MET) : 0.250ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.436ns (logic 0.141ns (32.314%) route 0.295ns (67.686%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.280ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.295 1.408 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X111Y48 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.914 1.280 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X111Y48 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
|
|
clock pessimism -0.030 1.250
|
|
SLICE_X111Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.158 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.158
|
|
arrival time 1.408
|
|
-------------------------------------------------------------------
|
|
slack 0.250
|
|
|
|
Slack (MET) : 0.254ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.040%) route 0.299ns (67.960%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.280ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.299 1.412 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X110Y48 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.914 1.280 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X110Y48 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/C
|
|
clock pessimism -0.030 1.250
|
|
SLICE_X110Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.158 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.158
|
|
arrival time 1.412
|
|
-------------------------------------------------------------------
|
|
slack 0.254
|
|
|
|
Slack (MET) : 0.254ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rdmux_sel_r_reg[0]/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.440ns (logic 0.141ns (32.040%) route 0.299ns (67.960%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.278ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.280ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.299 1.412 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X110Y48 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rdmux_sel_r_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.914 1.280 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X110Y48 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rdmux_sel_r_reg[0]/C
|
|
clock pessimism -0.030 1.250
|
|
SLICE_X110Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.158 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rdmux_sel_r_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.158
|
|
arrival time 1.412
|
|
-------------------------------------------------------------------
|
|
slack 0.254
|
|
|
|
Slack (MET) : 0.296ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.481ns (logic 0.141ns (29.306%) route 0.340ns (70.694%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.279ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.340 1.453 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X109Y48 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.913 1.279 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X109Y48 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]/C
|
|
clock pessimism -0.030 1.249
|
|
SLICE_X109Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.157 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.157
|
|
arrival time 1.453
|
|
-------------------------------------------------------------------
|
|
slack 0.296
|
|
|
|
Slack (MET) : 0.296ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[1]/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.481ns (logic 0.141ns (29.306%) route 0.340ns (70.694%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.279ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.340 1.453 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X109Y48 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.913 1.279 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X109Y48 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[1]/C
|
|
clock pessimism -0.030 1.249
|
|
SLICE_X109Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.157 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_den_r_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.157
|
|
arrival time 1.453
|
|
-------------------------------------------------------------------
|
|
slack 0.296
|
|
|
|
Slack (MET) : 0.296ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.481ns (logic 0.141ns (29.306%) route 0.340ns (70.694%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.279ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.340 1.453 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X109Y48 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.913 1.279 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X109Y48 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/C
|
|
clock pessimism -0.030 1.249
|
|
SLICE_X109Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.157 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.157
|
|
arrival time 1.453
|
|
-------------------------------------------------------------------
|
|
slack 0.296
|
|
|
|
Slack (MET) : 0.296ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[1]/CLR
|
|
(removal check against rising-edge clock clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns)
|
|
Data Path Delay: 0.481ns (logic 0.141ns (29.306%) route 0.340ns (70.694%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.277ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 1.279ns
|
|
Source Clock Delay (SCD): 0.972ns
|
|
Clock Pessimism Removal (CPR): 0.030ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.310 0.310 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.336 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.636 0.972 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
|
|
SLICE_X109Y51 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X109Y51 FDRE (Prop_fdre_C_Q) 0.141 1.113 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
|
|
net (fo=182, routed) 0.340 1.453 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
|
|
SLICE_X109Y48 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock clk_fpga_0 rise edge)
|
|
0.000 0.000 r
|
|
PS7_X0Y0 PS7 0.000 0.000 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0]
|
|
net (fo=1, routed) 0.337 0.337 u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0]
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 0.366 r u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O
|
|
net (fo=36463, routed) 0.913 1.279 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
|
|
SLICE_X109Y48 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[1]/C
|
|
clock pessimism -0.030 1.249
|
|
SLICE_X109Y48 FDCE (Remov_fdce_C_CLR) -0.092 1.157 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.157
|
|
arrival time 1.453
|
|
-------------------------------------------------------------------
|
|
slack 0.296
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
To Clock: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 28.554ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.361ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 28.554ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.036ns (logic 0.979ns (24.259%) route 3.057ns (75.741%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.516 7.602 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y59 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y59 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X111Y59 FDCE (Recov_fdce_C_CLR) -0.331 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 36.156
|
|
arrival time -7.602
|
|
-------------------------------------------------------------------
|
|
slack 28.554
|
|
|
|
Slack (MET) : 28.554ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.036ns (logic 0.979ns (24.259%) route 3.057ns (75.741%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.516 7.602 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y59 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y59 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X111Y59 FDCE (Recov_fdce_C_CLR) -0.331 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 36.156
|
|
arrival time -7.602
|
|
-------------------------------------------------------------------
|
|
slack 28.554
|
|
|
|
Slack (MET) : 28.554ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.036ns (logic 0.979ns (24.259%) route 3.057ns (75.741%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.516 7.602 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y59 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y59 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X111Y59 FDCE (Recov_fdce_C_CLR) -0.331 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 36.156
|
|
arrival time -7.602
|
|
-------------------------------------------------------------------
|
|
slack 28.554
|
|
|
|
Slack (MET) : 28.554ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.036ns (logic 0.979ns (24.259%) route 3.057ns (75.741%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.516 7.602 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y59 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y59 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X111Y59 FDCE (Recov_fdce_C_CLR) -0.331 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 36.156
|
|
arrival time -7.602
|
|
-------------------------------------------------------------------
|
|
slack 28.554
|
|
|
|
Slack (MET) : 28.554ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.036ns (logic 0.979ns (24.259%) route 3.057ns (75.741%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.516 7.602 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y59 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y59 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X111Y59 FDCE (Recov_fdce_C_CLR) -0.331 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 36.156
|
|
arrival time -7.602
|
|
-------------------------------------------------------------------
|
|
slack 28.554
|
|
|
|
Slack (MET) : 28.554ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.036ns (logic 0.979ns (24.259%) route 3.057ns (75.741%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.516 7.602 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y59 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y59 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X111Y59 FDCE (Recov_fdce_C_CLR) -0.331 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 36.156
|
|
arrival time -7.602
|
|
-------------------------------------------------------------------
|
|
slack 28.554
|
|
|
|
Slack (MET) : 28.554ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 4.036ns (logic 0.979ns (24.259%) route 3.057ns (75.741%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.044ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.156ns = ( 36.156 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.516 7.602 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y59 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.416 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y59 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/C
|
|
clock pessimism 0.366 36.522
|
|
clock uncertainty -0.035 36.487
|
|
SLICE_X111Y59 FDCE (Recov_fdce_C_CLR) -0.331 36.156 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 36.156
|
|
arrival time -7.602
|
|
-------------------------------------------------------------------
|
|
slack 28.554
|
|
|
|
Slack (MET) : 28.662ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 3.927ns (logic 0.979ns (24.931%) route 2.948ns (75.069%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.045ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.155ns = ( 36.155 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.407 7.493 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y60 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.415 36.155 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y60 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
|
|
clock pessimism 0.366 36.521
|
|
clock uncertainty -0.035 36.486
|
|
SLICE_X111Y60 FDCE (Recov_fdce_C_CLR) -0.331 36.155 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 36.155
|
|
arrival time -7.493
|
|
-------------------------------------------------------------------
|
|
slack 28.662
|
|
|
|
Slack (MET) : 28.662ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 3.927ns (logic 0.979ns (24.931%) route 2.948ns (75.069%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.045ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.155ns = ( 36.155 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.407 7.493 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y60 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.415 36.155 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y60 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
|
|
clock pessimism 0.366 36.521
|
|
clock uncertainty -0.035 36.486
|
|
SLICE_X111Y60 FDCE (Recov_fdce_C_CLR) -0.331 36.155 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 36.155
|
|
arrival time -7.493
|
|
-------------------------------------------------------------------
|
|
slack 28.662
|
|
|
|
Slack (MET) : 28.662ns (required time - arrival time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
(rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
|
|
(recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 33.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@33.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 3.927ns (logic 0.979ns (24.931%) route 2.948ns (75.069%))
|
|
Logic Levels: 3 (LUT1=1 LUT4=1 LUT6=1)
|
|
Clock Path Skew: -0.045ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 3.155ns = ( 36.155 - 33.000 )
|
|
Source Clock Delay (SCD): 3.566ns
|
|
Clock Pessimism Removal (CPR): 0.366ns
|
|
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.000ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.925 1.925 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.085 2.010 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.556 3.566 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
|
|
SLICE_X107Y75 FDRE r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X107Y75 FDRE (Prop_fdre_C_Q) 0.348 3.914 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[0]/Q
|
|
net (fo=1, routed) 0.632 4.546 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[0]
|
|
SLICE_X106Y75 LUT6 (Prop_lut6_I2_O) 0.242 4.788 f dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
|
|
net (fo=5, routed) 0.719 5.507 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
|
|
SLICE_X108Y75 LUT4 (Prop_lut4_I3_O) 0.125 5.632 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
|
|
net (fo=2, routed) 1.190 6.822 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
|
|
SLICE_X109Y62 LUT1 (Prop_lut1_I0_O) 0.264 7.086 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET[15]_i_2/O
|
|
net (fo=10, routed) 0.407 7.493 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iSEL_n
|
|
SLICE_X111Y60 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
33.000 33.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 33.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.663 34.663 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.077 34.740 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 1.415 36.155 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
|
|
SLICE_X111Y60 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
|
|
clock pessimism 0.366 36.521
|
|
clock uncertainty -0.035 36.486
|
|
SLICE_X111Y60 FDCE (Recov_fdce_C_CLR) -0.331 36.155 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 36.155
|
|
arrival time -7.493
|
|
-------------------------------------------------------------------
|
|
slack 28.662
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.285ns (logic 0.164ns (57.544%) route 0.121ns (42.456%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.121 1.948 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
|
|
SLICE_X111Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X111Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.948
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.285ns (logic 0.164ns (57.544%) route 0.121ns (42.456%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.121 1.948 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
|
|
SLICE_X111Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X111Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.948
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.285ns (logic 0.164ns (57.544%) route 0.121ns (42.456%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.121 1.948 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
|
|
SLICE_X111Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X111Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.948
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.285ns (logic 0.164ns (57.544%) route 0.121ns (42.456%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.121 1.948 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
|
|
SLICE_X111Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X111Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.948
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.285ns (logic 0.164ns (57.544%) route 0.121ns (42.456%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.121 1.948 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
|
|
SLICE_X111Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X111Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.948
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.285ns (logic 0.164ns (57.544%) route 0.121ns (42.456%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.121 1.948 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
|
|
SLICE_X111Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X111Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.948
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
Slack (MET) : 0.361ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[2]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.285ns (logic 0.164ns (57.544%) route 0.121ns (42.456%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.121 1.948 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
|
|
SLICE_X111Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
|
SLICE_X111Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[2]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X111Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.948
|
|
-------------------------------------------------------------------
|
|
slack 0.361
|
|
|
|
Slack (MET) : 0.365ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.289ns (logic 0.164ns (56.800%) route 0.125ns (43.200%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.125 1.951 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
|
|
SLICE_X110Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
|
|
SLICE_X110Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X110Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.951
|
|
-------------------------------------------------------------------
|
|
slack 0.365
|
|
|
|
Slack (MET) : 0.365ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.289ns (logic 0.164ns (56.800%) route 0.125ns (43.200%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.125 1.951 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
|
|
SLICE_X110Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
|
|
SLICE_X110Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X110Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.951
|
|
-------------------------------------------------------------------
|
|
slack 0.365
|
|
|
|
Slack (MET) : 0.365ns (arrival time - required time)
|
|
Source: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Destination: dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/CLR
|
|
(removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK {rise@0.000ns fall@16.500ns period=33.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise@0.000ns)
|
|
Data Path Delay: 0.289ns (logic 0.164ns (56.800%) route 0.125ns (43.200%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.069ns
|
|
Source Clock Delay (SCD): 1.663ns
|
|
Clock Pessimism Removal (CPR): 0.390ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 0.998 0.998 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 1.024 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.639 1.663 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
|
|
SLICE_X112Y41 FDPE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X112Y41 FDPE (Prop_fdpe_C_Q) 0.164 1.827 f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
|
|
net (fo=16, routed) 0.125 1.951 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
|
|
SLICE_X110Y41 FDCE f dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK rise edge)
|
|
0.000 0.000 r
|
|
BSCAN_X0Y0 BSCANE2 0.000 0.000 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
|
|
net (fo=1, routed) 1.130 1.130 dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
|
|
BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 1.159 r dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
|
|
net (fo=486, routed) 0.910 2.069 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
|
|
SLICE_X110Y41 FDCE r dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
|
|
clock pessimism -0.390 1.679
|
|
SLICE_X110Y41 FDCE (Remov_fdce_C_CLR) -0.092 1.587 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.587
|
|
arrival time 1.951
|
|
-------------------------------------------------------------------
|
|
slack 0.365
|
|
|
|
|
|
|
|
|
|
|