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BSI-901-fpga-software/c64_pro.runs/c_add_s16_s32_synth_1/runme.log
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*** Running vivado
with args -log c_add_s16_s32.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source c_add_s16_s32.tcl
****** Vivado v2023.1 (64-bit)
**** SW Build 3865809 on Sun May 7 15:05:29 MDT 2023
**** IP Build 3864474 on Sun May 7 20:36:21 MDT 2023
**** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
source c_add_s16_s32.tcl -notrace
create_project: Time (s): cpu = 00:00:11 ; elapsed = 00:00:12 . Memory (MB): peak = 1469.449 ; gain = 160.047
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: c_add_s16_s32
Command: synth_design -top c_add_s16_s32 -part xc7z020clg400-2 -incremental_mode off -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Device 21-403] Loading part xc7z020clg400-2
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 34700
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2322.395 ; gain = 409.438
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'c_add_s16_s32' [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/synth/c_add_s16_s32.vhd:70]
Parameter C_VERBOSITY bound to: 0 - type: integer
Parameter C_XDEVICEFAMILY bound to: zynq - type: string
Parameter C_IMPLEMENTATION bound to: 0 - type: integer
Parameter C_A_WIDTH bound to: 16 - type: integer
Parameter C_B_WIDTH bound to: 32 - type: integer
Parameter C_OUT_WIDTH bound to: 32 - type: integer
Parameter C_CE_OVERRIDES_SCLR bound to: 0 - type: integer
Parameter C_A_TYPE bound to: 0 - type: integer
Parameter C_B_TYPE bound to: 0 - type: integer
Parameter C_LATENCY bound to: 1 - type: integer
Parameter C_ADD_MODE bound to: 0 - type: integer
Parameter C_B_CONSTANT bound to: 0 - type: integer
Parameter C_B_VALUE bound to: 00000000000000000000000000000000 - type: string
Parameter C_AINIT_VAL bound to: 0 - type: string
Parameter C_SINIT_VAL bound to: 0 - type: string
Parameter C_CE_OVERRIDES_BYPASS bound to: 1 - type: integer
Parameter C_BYPASS_LOW bound to: 0 - type: integer
Parameter C_SCLR_OVERRIDES_SSET bound to: 1 - type: integer
Parameter C_HAS_C_IN bound to: 0 - type: integer
Parameter C_HAS_C_OUT bound to: 0 - type: integer
Parameter C_BORROW_LOW bound to: 1 - type: integer
Parameter C_HAS_CE bound to: 1 - type: integer
Parameter C_HAS_BYPASS bound to: 0 - type: integer
Parameter C_HAS_SCLR bound to: 1 - type: integer
Parameter C_HAS_SSET bound to: 0 - type: integer
Parameter C_HAS_SINIT bound to: 0 - type: integer
INFO: [Synth 8-3491] module 'c_addsub_v12_0_15' declared at 'd:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/hdl/c_addsub_v12_0_vh_rfs.vhd:7029' bound to instance 'U0' of component 'c_addsub_v12_0_15' [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/synth/c_add_s16_s32.vhd:139]
INFO: [Synth 8-256] done synthesizing module 'c_add_s16_s32' (0#1) [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/synth/c_add_s16_s32.vhd:70]
WARNING: [Synth 8-7129] Port AINIT in module c_reg_fd_v12_0_6_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port ACLR in module c_reg_fd_v12_0_6_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port ASET in module c_reg_fd_v12_0_6_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port SINIT in module c_reg_fd_v12_0_6_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port SSET in module c_reg_fd_v12_0_6_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port add in module c_addsub_v12_0_15_lut6_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port c_in in module c_addsub_v12_0_15_lut6_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port bypass in module c_addsub_v12_0_15_lut6_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port sset in module c_addsub_v12_0_15_lut6_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port sinit in module c_addsub_v12_0_15_lut6_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port c_in in module c_addsub_v12_0_15_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port b_in in module c_addsub_v12_0_15_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port a_signed in module c_addsub_v12_0_15_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port b_signed in module c_addsub_v12_0_15_legacy is either unconnected or has no load
WARNING: [Synth 8-7129] Port C_IN in module c_addsub_v12_0_15_viv is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2438.066 ; gain = 525.109
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
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---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2455.980 ; gain = 543.023
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2455.980 ; gain = 543.023
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 2467.992 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 63 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
Initializing timing engine
Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_ooc.xdc] for cell 'U0'
Finished Parsing XDC File [d:/Project/spinal_stim/pl/spinal_stim_v0/LJS.gen/sources_1/ip/c_add_s16_s32/c_add_s16_s32_ooc.xdc] for cell 'U0'
Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/c_add_s16_s32_synth_1/dont_touch.xdc]
Finished Parsing XDC File [D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/c_add_s16_s32_synth_1/dont_touch.xdc]
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2550.520 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2550.520 ; gain = 0.000
INFO: [Designutils 20-5008] Incremental synthesis strategy off
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Finished Constraint Validation : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2550.520 ; gain = 637.562
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Start Loading Part and Timing Information
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Loading part: xc7z020clg400-2
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/c_add_s16_s32_synth_1/dont_touch.xdc, line 9).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2550.520 ; gain = 637.562
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Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:29 ; elapsed = 00:00:30 . Memory (MB): peak = 2550.520 ; gain = 637.562
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Start RTL Component Statistics
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Finished RTL Component Statistics
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Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 220 (col length:60)
BRAMs: 280 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port ADD in module c_addsub_v12_0_15_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port C_IN in module c_addsub_v12_0_15_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port BYPASS in module c_addsub_v12_0_15_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port SSET in module c_addsub_v12_0_15_viv is either unconnected or has no load
WARNING: [Synth 8-7129] Port SINIT in module c_addsub_v12_0_15_viv is either unconnected or has no load
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
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---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:40 ; elapsed = 00:00:42 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
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Start IO Insertion
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Start Flattening Before IO Insertion
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Finished Flattening Before IO Insertion
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---------------------------------------------------------------------------------
Start Final Netlist Cleanup
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Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
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---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
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Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
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---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
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Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
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Finished Renaming Generated Nets : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
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Start Writing Synthesis Report
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Report BlackBoxes:
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+
Report Cell Usage:
+------+------+------+
| |Cell |Count |
+------+------+------+
|1 |LUT2 | 32|
|2 |MUXCY | 31|
|3 |XORCY | 32|
|4 |FDRE | 32|
+------+------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 6 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:29 ; elapsed = 00:00:47 . Memory (MB): peak = 2550.520 ; gain = 543.023
Synthesis Optimization Complete : Time (s): cpu = 00:00:49 ; elapsed = 00:00:50 . Memory (MB): peak = 2550.520 ; gain = 637.562
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2550.520 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 63 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 2550.520 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
A total of 8 instances were transformed.
(MUXCY,XORCY) => CARRY4: 8 instances
Synth Design complete | Checksum: ec045e2a
INFO: [Common 17-83] Releasing license: Synthesis
21 Infos, 21 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:55 ; elapsed = 00:00:59 . Memory (MB): peak = 2550.520 ; gain = 1042.918
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/c_add_s16_s32_synth_1/c_add_s16_s32.dcp' has been generated.
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP c_add_s16_s32, cache-ID = 1e64087ccacaee48
INFO: [Coretcl 2-1174] Renamed 6 cell refs.
INFO: [Common 17-1381] The checkpoint 'D:/Project/spinal_stim/pl/spinal_stim_v0/c64_pro.runs/c_add_s16_s32_synth_1/c_add_s16_s32.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file c_add_s16_s32_utilization_synth.rpt -pb c_add_s16_s32_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Wed Jun 24 13:53:35 2026...
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