`timescale 1ns/1ps
 
module channel_switch_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	localparam 		T_CLK 			= 10	;		//ns
	
	localparam		DATA_WIDTH		= 64    ;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg							clk			;
	reg							rst_n		;
	
	reg		[64-1:0]	        data_0		;
	reg		[64-1:0]	        data_1		;
	wire	[64-1:0]	        state		;
	
	wire						adg1414_spi_cs   	;
	wire						adg1414_spi_sclk   	;
	wire						adg1414_spi_mosi   	;
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
        #100;
		
		@ ( posedge clk );
		data_0 <= 64'h8000000000000002;

		while (1) begin
			@ ( posedge clk );
		//	data_0 <= data_0 + 1'b1;
			#5_000;
		end
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk		<= 1'b0	;
			rst_n	<= 1'b0	;
			
			data_0	<= 64'h0000000000000000;
			data_1	<= 64'hFFFFFFFFFFFFFFFF;
		end
	endtask	
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	channel_switch# 
		(
			.CLK_PERIOD		    ( T_CLK     			)
		)
	DUT
		(
			.clk			    ( clk 			        ),
			.rst_n			    ( rst_n 		        ),
			
			.enable			    ( 1'b1					),
			.data_sel		    ( 1'b0					),
			.data_0			    ( data_0				),
			.data_1			    ( data_1				),
			.state			    ( state					),
			
			.sync			    ( adg1414_spi_cs   		),
			.sclk			    ( adg1414_spi_sclk   	),
			.sdin			    ( adg1414_spi_mosi   	),
			.sdo			    ( 1'b0   				)
		);
	
endmodule