`timescale 1 ns / 1 ps

module channel_switch#
	(
		parameter	CLK_PERIOD	= 10
	)
	(
		input					clk			,
		input					rst_n		,
		
		input					enable		,
		input					data_sel	,
		input		[64-1:0]	data_0		,
		input		[64-1:0]	data_1		,
		output		[64-1:0]	state		,
		
		output					sync		,
		output					sclk		,
		output					sdin		,
		input					sdo
	);
	
	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	localparam 	IDLE		= 4'b0000		;
	localparam 	MON_ST		= 4'd0001		;
	localparam 	CFG_ST		= 4'd0011		;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg		[64-1:0]		new_data				;
	wire	[64-1:0]		new_data_map			;
	reg		[64-1:0]		new_data_r				;
	reg		[64-1:0]		cur_data				;

	reg		[ 4-1:0]		cstate					;

	wire					s_tready				;
	reg						s_tvalid				;
	reg		[64-1:0]		s_tdata     			;

//	wire	[64-1:0]		probe_out0				;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	adg1414_if# 
		(
			.CLK_PERIOD		    ( CLK_PERIOD		),
			.CLK_DIV		    ( 20				),
			.DATA_WIDTH		    ( 64				)
		)
	u_adg1414_if
		(
			.clk			    ( clk				),
			.rst_n			    ( rst_n				),

			.s_tready		    ( s_tready			),
			.s_tvalid		    ( s_tvalid			),
			.s_tdata		    ( s_tdata			),
			
			.sync			    ( sync				),
			.sclk			    ( sclk				),
			.sdin			    ( sdin				)
		);

	// vio_0 vio_0_switch
	// 	(
	// 		.clk				( clk				),	// input wire clk

	// 		.probe_in0			( enable			),	// input wire [0 : 0] probe_in0
	// 		.probe_in1			( data_sel			),	// input wire [0 : 0] probe_in1
	// 		.probe_in2			( data_0			),	// input wire [63 : 0] probe_in2
	// 		.probe_in3			( data_1			),	// input wire [63 : 0] probe_in3
	// 		.probe_in4			( new_data			),	// input wire [63 : 0] probe_in4
	// 		.probe_in5			( state				),	// input wire [63 : 0] probe_in5

	// 		.probe_out0			( probe_out0		)	// output wire [63 : 0] probe_out0
	// 	);
		
	//*****************************************************************************
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			new_data <= 0;
		else if (!data_sel)
			new_data = data_0;//probe_out0;//
		else
			new_data = data_1;
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n ) begin
			cstate <= 4'd0;
		end else begin
			case (cstate)
				IDLE:
					if ( enable )
						cstate <= MON_ST;
					else
						cstate <= IDLE;
				MON_ST:
					if ( !enable )
						cstate <= IDLE;
					else if (cur_data != new_data_map)
						cstate <= CFG_ST;
					else
						cstate <= MON_ST;
				CFG_ST:
					if ( s_tvalid && s_tready )
						cstate <= IDLE;
				default:
					cstate <= IDLE;
			endcase
		end
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			new_data_r <= 0;
		else if (enable && cstate == MON_ST)
			new_data_r <= new_data_map;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n ) begin
			s_tvalid <= 1'b0;
			s_tdata <= 0;
		end else if ( s_tvalid && s_tready ) begin
			s_tvalid <= 1'b0;
		end else if ( cstate == CFG_ST ) begin
			s_tvalid <= 1'b1;
			s_tdata <= new_data_r;
		end
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n ) begin
			cur_data <= 0;
		end else if ( s_tvalid && s_tready ) begin
			cur_data <= s_tdata;
		end
	end
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	assign state = cur_data;

	assign new_data_map[ 6] = new_data[ 0];
	assign new_data_map[ 7] = new_data[ 1];
	assign new_data_map[ 5] = new_data[ 2];
	assign new_data_map[ 4] = new_data[ 3];
	assign new_data_map[ 3] = new_data[ 4];
	assign new_data_map[ 2] = new_data[ 5];
	assign new_data_map[ 1] = new_data[ 6];
	assign new_data_map[ 0] = new_data[ 7];

	assign new_data_map[14] = new_data[ 8];
	assign new_data_map[15] = new_data[ 9];
	assign new_data_map[13] = new_data[10];
	assign new_data_map[11] = new_data[11];
	assign new_data_map[ 8] = new_data[12];
	assign new_data_map[10] = new_data[13];
	assign new_data_map[ 9] = new_data[14];
	assign new_data_map[12] = new_data[15];

	assign new_data_map[38] = new_data[16];
	assign new_data_map[39] = new_data[17];
	assign new_data_map[37] = new_data[18];
	assign new_data_map[36] = new_data[19];
	assign new_data_map[35] = new_data[20];
	assign new_data_map[34] = new_data[21];
	assign new_data_map[33] = new_data[22];
	assign new_data_map[32] = new_data[23];

	assign new_data_map[46] = new_data[24];
	assign new_data_map[47] = new_data[25];
	assign new_data_map[45] = new_data[26];
	assign new_data_map[43] = new_data[27];
	assign new_data_map[40] = new_data[28];
	assign new_data_map[42] = new_data[29];
	assign new_data_map[41] = new_data[30];
	assign new_data_map[44] = new_data[31];

	assign new_data_map[22] = new_data[32];
	assign new_data_map[23] = new_data[33];
	assign new_data_map[21] = new_data[34];
	assign new_data_map[20] = new_data[35];
	assign new_data_map[19] = new_data[36];
	assign new_data_map[18] = new_data[37];
	assign new_data_map[17] = new_data[38];
	assign new_data_map[16] = new_data[39];

	assign new_data_map[30] = new_data[40];
	assign new_data_map[31] = new_data[41];
	assign new_data_map[29] = new_data[42];
	assign new_data_map[27] = new_data[43];
	assign new_data_map[24] = new_data[44];
	assign new_data_map[26] = new_data[45];
	assign new_data_map[25] = new_data[46];
	assign new_data_map[28] = new_data[47];

	assign new_data_map[54] = new_data[48];
	assign new_data_map[55] = new_data[49];
	assign new_data_map[53] = new_data[50];
	assign new_data_map[52] = new_data[51];
	assign new_data_map[50] = new_data[52];
	assign new_data_map[51] = new_data[53];
	assign new_data_map[49] = new_data[54];
	assign new_data_map[48] = new_data[55];

	assign new_data_map[62] = new_data[56];
	assign new_data_map[63] = new_data[57];
	assign new_data_map[61] = new_data[58];
	assign new_data_map[59] = new_data[59];
	assign new_data_map[56] = new_data[60];
	assign new_data_map[58] = new_data[61];
	assign new_data_map[57] = new_data[62];
	assign new_data_map[60] = new_data[63];
	
endmodule