`timescale 1 ns / 1 ps

module cnv_res_collect#
	(
		parameter							CLK_PERIOD		= 10	,
		parameter							CHIPSET_QTY		=  4	,
		parameter							CH_OF_CHIPSET	= 16
	)
	(
		input								clk						,
		input								rst_n					,

		input								trans_round				,	//TODO: use for 'axi_str_rxd_tlast'
		input		[16-1:0]				record_ch_qty			,
		
		input		[32*CHIPSET_QTY-1:0]	cnv_res_tdata_array		,
		input		[   CHIPSET_QTY-1:0]	cnv_res_tlast_array		,
		output	reg	[   CHIPSET_QTY-1:0]	cnv_res_tready_array	,
		input		[   CHIPSET_QTY-1:0]	cnv_res_tvalid_array	,
		
		output	reg	[31:0]					m_axis_eeg_tdata		,
		output	reg							m_axis_eeg_tlast		,
		input								m_axis_eeg_tready		,
		output	reg							m_axis_eeg_tvalid
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	IDLE				= 4'd0				;
	localparam 	SCAN_ST				= 4'd1				;
	
	localparam 	CHANNEL_QTY			= CH_OF_CHIPSET*CHIPSET_QTY			;	//2^6: 0~63
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg		[ 4-1:0]				cstate								;
	reg		[ 4-1:0]				nstate								;
	
	wire	[32-1:0]				cnv_res_tdata[0:CHIPSET_QTY-1]		;
	wire							cnv_res_tlast[0:CHIPSET_QTY-1]		;
	wire							cnv_res_tready[0:CHIPSET_QTY-1]		;
	wire							cnv_res_tvalid[0:CHIPSET_QTY-1]		;
	
	reg		[32-1:0]				cnv_res_tdata_r[0:CHIPSET_QTY-1]	;
	reg								cnv_res_tvalid_r[0:CHIPSET_QTY-1]	;
	reg								cnv_res_tlast_r[0:CHIPSET_QTY-1]	;
	
	reg		[ 8-1:0]				scan_cnt							;
	reg		[ 8-1:0]				recv_cnt							;
	
	genvar	i;
	
	//*****************************************************************************

	always@( posedge clk or negedge rst_n ) begin
		if( !rst_n )	cstate <= IDLE;
		else        	cstate <= nstate;
	end
	
	always@( * ) begin
		case ( cstate )
			IDLE:
				if ( cnv_res_tvalid_array )
					nstate 	<= SCAN_ST;
				else
					nstate 	<= IDLE;
			SCAN_ST:
				if ( scan_cnt == CHIPSET_QTY-1 )
					nstate 	<= IDLE;
				else
					nstate 	<= SCAN_ST;
			default:
				nstate 	<= IDLE;
		endcase	
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			cnv_res_tready_array <= 0;
		else if ( cstate == IDLE && nstate == IDLE )
			cnv_res_tready_array <= {CHIPSET_QTY{1'b1}};
		else
			cnv_res_tready_array <= 0;
	end
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : rx_data
			always @ ( posedge clk or negedge rst_n ) begin
				if ( !rst_n ) begin
					cnv_res_tdata_r[i]	<= 0;
					cnv_res_tvalid_r[i]	<= 1'b0;
					cnv_res_tlast_r[i]	<= 1'b0;
				end else if ( cnv_res_tready[i] && cnv_res_tvalid[i] ) begin
					cnv_res_tdata_r[i]	<= cnv_res_tdata[i];
					cnv_res_tvalid_r[i]	<= cnv_res_tvalid[i];
					cnv_res_tlast_r[i]	<= cnv_res_tlast[i];
				end else if ( cstate == IDLE ) begin
					cnv_res_tvalid_r[i]	<= 1'b0;
				end
			end
		end
	endgenerate
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			scan_cnt <= 0;
		else if ( cstate == IDLE )
			scan_cnt <= 0;
		else if ( cstate == SCAN_ST )
			scan_cnt <= scan_cnt + 1'b1;
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			recv_cnt <= 0;
		else if ( trans_round )
			recv_cnt <= 0;
		else if ( cstate == SCAN_ST && cnv_res_tvalid_r[scan_cnt] )
			recv_cnt <= recv_cnt + 1'b1;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n ) begin
			m_axis_eeg_tdata <= 0;
			m_axis_eeg_tvalid <= 1'b0;
		end else if ( cstate == SCAN_ST ) begin
			m_axis_eeg_tdata <= cnv_res_tdata_r[scan_cnt];
			m_axis_eeg_tvalid <= cnv_res_tvalid_r[scan_cnt];
		end else begin
			m_axis_eeg_tvalid <= 1'b0;
		end
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			m_axis_eeg_tlast <= 1'b0;
		else if ( cstate == SCAN_ST && cnv_res_tvalid_r[scan_cnt] && (recv_cnt+1 == record_ch_qty) )
			m_axis_eeg_tlast <= 1'b1;
		else
			m_axis_eeg_tlast <= 1'b0;
	end
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack_res
		//	assign cnv_res_tdata[i][15: 0] = cnv_res_tdata_array[32*i+31 : 32*i+16];
		//	assign cnv_res_tdata[i][21:16] = cnv_res_tdata_array[32*i+15 : 32*i+10] + CH_OF_CHIPSET*i;
		//	assign cnv_res_tdata[i][30:22] = {9{1'b0}};
		//	assign cnv_res_tdata[i][31   ] = cnv_res_tdata_array[32*i+ 0];
			assign cnv_res_tdata[i][31:16] = cnv_res_tdata_array[32*i+31 : 32*i+16];
			assign cnv_res_tdata[i][15:10] = cnv_res_tdata_array[32*i+15 : 32*i+10] + CH_OF_CHIPSET*i;
			assign cnv_res_tdata[i][ 9: 1] = {9{1'b0}};
			assign cnv_res_tdata[i][    0] = cnv_res_tdata_array[32*i+ 0];
			assign cnv_res_tlast[i] = cnv_res_tlast_array[i];
			assign cnv_res_tvalid[i] = cnv_res_tvalid_array[i];
			assign cnv_res_tready[i] = cnv_res_tready_array[i];
		end
	endgenerate
	
endmodule