`timescale 1ns/1ps
 
module eeg_top_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	localparam	T_CLK 			= 10;		//ns
	
    localparam	SPIS_QTY		=  4;
    localparam	CHIPSET_QTY		=  8;
	
	localparam 	BRAM_ADDR_TEST_RO				= 13'h0000;
	localparam 	BRAM_ADDR_TEST_RW				= 13'h0004;
	
	localparam 	BRAM_ADDR_EEG_ER				= 13'h0040;
	localparam 	BRAM_ADDR_EEG_CR				= 13'h0044;
	localparam 	BRAM_ADDR_EEG_SR				= 13'h0048;
	localparam 	BRAM_ADDR_EEG_TR				= 13'h0100;
	localparam 	BRAM_ADDR_EEG_RR				= 13'h0200;
	
	localparam 	BRAM_ADDR_EEG_TR_MASK			= 13'h1F00;
	localparam 	BRAM_ADDR_EEG_RR_MASK			= 13'h1F00;

	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg								clk					;
	reg								rst_n				;
	
	reg		[13-1:0]				bram_eeg_addr		;
	reg								bram_eeg_clk		;
	reg		[32-1:0]				bram_eeg_din		;
	wire	[32-1:0]				bram_eeg_dout		;
	reg								bram_eeg_en			;
	reg								bram_eeg_rst		;
	reg		[ 4-1:0]				bram_eeg_we			;

    wire							interrupt			;

	reg		[32-1:0]				trigger_tdata		;
	reg								trigger_tvalid		;
	
	reg		[32-1:0]				read_data			;

    wire	[32-1:0]				axis_record_tdata	;
    wire							axis_record_tlast	;
    reg							    axis_record_tready	;
    wire							axis_record_tvalid	;
    
    wire	[CHIPSET_QTY-1:0]		cs_w				;
    wire	[   SPIS_QTY-1:0]		sclk_w				;
    wire	[   SPIS_QTY-1:0]		mosi_w				;
    wire	[   SPIS_QTY-1:0]		miso_w				;
    wire	[   SPIS_QTY-1:0]		drdy_w				;
    wire							start_w				;

    wire	[CHIPSET_QTY-1:0]		cs					;
    wire	[CHIPSET_QTY-1:0]		sclk				;
    wire    [CHIPSET_QTY-1:0]		mosi				;
    wire	[CHIPSET_QTY-1:0]		miso				;
    wire	[CHIPSET_QTY-1:0]		drdy				;
    wire	[CHIPSET_QTY-1:0]		start               ;
	
	integer n;
	genvar	i;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	eeg_top#
		(
			.CLK_PERIOD			( T_CLK			        )
		)
	DUT
		(
			.clk				( clk					),
			.rst_n				( rst_n					),
			
			.bram_addr			( bram_eeg_addr			),
			.bram_clk			( bram_eeg_clk			),
			.bram_din			( bram_eeg_din			),
			.bram_dout			( bram_eeg_dout			),
			.bram_en			( bram_eeg_en			),
			.bram_rst			( bram_eeg_rst			),
			.bram_we			( bram_eeg_we			),

			.interrupt			( interrupt				),

			.trigger_tdata		( trigger_tdata			),
			.trigger_tvalid		( trigger_tvalid		),
			
			//------------------------------------------ FIFO: eeg output
			.axis_record_tdata	( axis_record_tdata		),
			.axis_record_tlast	( axis_record_tlast     ),
			.axis_record_tready	( axis_record_tready    ),
			.axis_record_tvalid	( axis_record_tvalid    ),
			
			//------------------------------------------ device spi
			.cs					( cs_w	                ),
			.sclk				( sclk_w	            ),
			.mosi				( mosi_w	            ),
			.miso				( miso_w	            ),
			.drdy				( drdy_w	            ),
			.start				( start_w	            )
		);
	
	generate
		for(i=0; i<CHIPSET_QTY; i=i+1) begin : spi
			ads1299_mod u_ads1299_mod
				(
					.cs		( cs[i]		),
					.sclk	( sclk[i]	),
					.mosi	( mosi[i]	),
					.miso	( miso[i]	),
					.drdy	( drdy[i]	),
					.start	( start[i]	)
				);
		end
	endgenerate
	
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		#100
		
		/*
		//SDATAC
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00000011);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00000011);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00000011);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000011);
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100});
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
		#4_000
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101});
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
		#4_000

		//READ ID
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b1100, 4'b1100, 4'b1100, 4'b1100});
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
		#10_000
		read_bram_eeg(BRAM_ADDR_EEG_RR+4'h0, read_data);
		#100
	//	$stop;

        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00010020);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00020020);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00030020);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00040020);
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b1101, 4'b1101, 4'b1101, 4'b1101});
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
		#10_000

		//
		#7_000
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0100, 4'b0100, 4'b0100, 4'b0100});
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
		
		#3_000
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h00, 32'h00000010);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h04, 32'h00000010);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h08, 32'h00000010);
		write_bram_eeg(BRAM_ADDR_EEG_TR + 8'h0C, 32'h00000010);
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_CR, {16'd0, 4'b0101, 4'b0101, 4'b0101, 4'b0101});
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_ER, 32'hF);
		*/

		#3_000
        @ ( posedge clk );
		write_bram_eeg(BRAM_ADDR_EEG_CR, {1'b1, 15'd10, 16'd0});

	//	#40_000
	//	@ ( posedge clk );
	//	$stop;
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk			<= 1'b0	;
			rst_n		<= 1'b0	;
			
			bram_eeg_addr	<= 0	;
			bram_eeg_clk	<= 1'b0	;
			bram_eeg_din	<= 0	;
			bram_eeg_en		<= 1'b0	;
			bram_eeg_rst	<= 1'b0	;
			bram_eeg_we		<= 0	;

			trigger_tdata	<= 0	;
			trigger_tvalid	<= 1'b0	;

            axis_record_tready  <= 1'b1;
			
		end
	endtask
	
	task read_bram_eeg;
		input [12:0] addr;
		output [31:0] data;
		begin
			@ ( posedge clk );
			bram_eeg_addr	<= addr;
			bram_eeg_en		<= 1;
			bram_eeg_we		<= 4'h0;
			@ ( posedge clk );
			bram_eeg_en		<= 0;
			@ ( posedge clk );
			data <= bram_eeg_dout;
		end
	endtask
	
	task write_bram_eeg;
		input [12:0] addr;
		input [31:0] data;
		begin
			@ ( posedge clk );
			bram_eeg_addr	<= addr;
			bram_eeg_din	<= data;
			bram_eeg_en		<= 1;
			bram_eeg_we		<= 4'hF;
			@ ( posedge clk );
			bram_eeg_en		<= 0;
			bram_eeg_we		<= 4'h0;
		end
	endtask
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
    
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : mapping_spi
			assign cs[i] = cs_w[i];
			assign sclk[i] = sclk_w[i/2];
			assign mosi[i] = mosi_w[i/2];
			assign start[i] = start_w;
		end
	endgenerate

	generate
		for(i=0;i<SPIS_QTY;i=i+1) begin : mapping_reg
			assign drdy_w[i] = drdy[2*i];
		end
	endgenerate

    assign miso_w[0] = (~cs_w[0])? miso[0]:((~cs_w[1])? miso[1]:1'bZ);
    assign miso_w[1] = (~cs_w[2])? miso[2]:((~cs_w[3])? miso[3]:1'bZ);
    assign miso_w[2] = (~cs_w[4])? miso[4]:((~cs_w[5])? miso[5]:1'bZ);
    assign miso_w[3] = (~cs_w[6])? miso[6]:((~cs_w[7])? miso[7]:1'bZ);

endmodule