`timescale 1ns/1ps
 
module ads1299_spi_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	parameter 		T_CLK 		= 20;		//ns
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg							clk			;
	reg							rst_n		;
	
	reg							trans 		;
	
	wire						rdy 		;
	reg							start 		;
	reg  [32 - 1:0]				din			;
	wire						done		;
	wire [32 - 1:0]				dout		;
	
	wire						cs			;
	wire						sclk		;
	wire						mosi		;
	wire						miso		;
	
	reg  [32 - 1:0]				data		;
	reg  [ 8 - 1:0]				cnt			;
	
	//GSR GSR(.GSRI(1'b1));
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			trans <= 1'b0	;
		else if (cs) begin
			#200 trans <= 1'b1;
			#20 trans <= 1'b0;
		end
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			start <= 1'b0;
			din   <= 0;
			data  <= 0;
		end else if ( trans ) begin
			start <= 1'b1;
			din   <= 32'hAAAA5555;//$random;
			data  <= 32'hCCCCAAA5;//$random;
		end else
			start <= 1'b0;
	end
	
	always @ ( negedge sclk or negedge rst_n or posedge cs ) begin
		if( !rst_n )
			cnt <= 8'd31;
		else if( cs )
			cnt <= 8'd31;
		else if ( cnt != 0 )
			cnt <= cnt - 1'b1;
	end
	
	assign miso = data[cnt];
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk			<= 1'b0	;
			rst_n		<= 1'b0	;
		end
	endtask	
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	ads1299_spi# 
		(
			.CLK_PERIOD	( 50			),
			.CLK_DIV	( 2				),
			.DATA_WIDTH	( 32			)
		)
	DUT
		(
			.clk		( clk 			),
			.rst_n		( rst_n 		),
			
			.rdy		( rdy 			),
			.start		( start			),
			.din		( din   		),
			.done		( done   		),
			.dout		( dout			),
			
			.cs			( cs   			),
			.sclk		( sclk   		),
			.mosi		( mosi   		),
			.miso		( miso   		)
		);
	
	
endmodule