Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
| Date             : Sun Aug  4 13:44:39 2024
| Host             : 840-5CG14025H4 running 64-bit major release  (build 9200)
| Command          : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
| Design           : c64pro_top
| Device           : xc7z010clg400-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 1.263        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 1.145        |
| Device Static (W)        | 0.118        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 70.4         |
| Junction Temperature (C) | 39.6         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.033 |        3 |       --- |             --- |
| Slice Logic              |     0.021 |    37606 |       --- |             --- |
|   LUT as Logic           |     0.019 |    11627 |     17600 |           66.06 |
|   CARRY4                 |    <0.001 |      565 |      4400 |           12.84 |
|   Register               |    <0.001 |    18749 |     35200 |           53.26 |
|   LUT as Distributed RAM |    <0.001 |      444 |      6000 |            7.40 |
|   F7/F8 Muxes            |    <0.001 |     1473 |     17600 |            8.37 |
|   LUT as Shift Register  |    <0.001 |      141 |      6000 |            2.35 |
|   BUFG                   |    <0.001 |        4 |        32 |           12.50 |
|   Others                 |     0.000 |     1299 |       --- |             --- |
| Signals                  |     0.033 |    26449 |       --- |             --- |
| Block RAM                |     0.012 |       26 |        60 |           43.33 |
| I/O                      |     0.003 |       76 |       100 |           76.00 |
| PS7                      |     1.043 |        1 |       --- |             --- |
| Static Power             |     0.118 |          |           |                 |
| Total                    |     1.263 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.105 |       0.098 |      0.007 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.007 |       0.000 |      0.007 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.002 |       0.001 |      0.001 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.003 |       0.001 |      0.002 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccpint   |       1.000 |     0.573 |       0.547 |      0.025 |       NA    | Unspecified | NA         |
| Vccpaux   |       1.800 |     0.035 |       0.025 |      0.010 |       NA    | Unspecified | NA         |
| Vccpll    |       1.800 |     0.018 |       0.015 |      0.003 |       NA    | Unspecified | NA         |
| Vcco_ddr  |       1.350 |     0.311 |       0.309 |      0.002 |       NA    | Unspecified | NA         |
| Vcco_mio0 |       3.300 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vcco_mio1 |       1.800 |     0.002 |       0.001 |      0.001 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+------------+--------------------------------------------------------------------------+-----------------+
| Clock      | Domain                                                                   | Constraint (ns) |
+------------+--------------------------------------------------------------------------+-----------------+
| clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] |            10.0 |
+------------+--------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+-------------------------------+-----------+
| Name                          | Power (W) |
+-------------------------------+-----------+
| c64pro_top                    |     1.145 |
|   u_pl_top                    |     0.043 |
|     u_eeg_top                 |     0.007 |
|       u_eeg_upload            |     0.002 |
|     u_rhs2116_top             |     0.017 |
|       u_sine_wave_gen         |     0.003 |
|       u_trans_distribute      |     0.003 |
|       u_transmit_config       |     0.005 |
|     u_upload_top              |     0.018 |
|       u_upload_config         |     0.005 |
|       u_upload_protocol_intan |     0.002 |
|       u_upload_protocol_ql    |     0.003 |
|       u_upload_sort           |     0.008 |
|   u_ps_a9_1                   |     1.098 |
|     design_a9_1_i             |     1.089 |
|       axi_dma_0               |     0.002 |
|       axi_dma_1               |     0.003 |
|       axi_iic_0               |     0.001 |
|       axi_iic_1               |     0.001 |
|       axi_smc                 |     0.010 |
|       axis_data_fifo_0        |     0.004 |
|       axis_data_fifo_1        |     0.006 |
|       processing_system7_0    |     1.043 |
|       smartconnect_0          |     0.016 |
+-------------------------------+-----------+