`timescale 1 ns / 1 ps

module stim_event_collect#
	(
		parameter			CHIPSET_QTY	= 4
	)
	(
		input							clk				,
		input							rst_n			,
		
		input	[32*CHIPSET_QTY-1:0]	event_in_arrary	,
		output	[32-1:0]				event_out
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	HOLD_CLKS				= CHIPSET_QTY		;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	wire	[32-1:0]			event_in[0:CHIPSET_QTY-1];
	reg		[32-1:0]			event_in_r[0:CHIPSET_QTY-1];
	reg							update[0:CHIPSET_QTY-1];
	reg		[ 4-1:0]			cnt[0:CHIPSET_QTY-1];
	reg		[32-1:0]			event_r;
	reg		[ 4-1:0]			n;

	genvar	i;
	
	//*****************************************************************************
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : rrr
			always @ ( posedge clk or negedge rst_n ) begin
				if ( !rst_n )
					event_in_r[i]	<= 0;
				else
					event_in_r[i]	<= event_in[i];
			end
		end
	endgenerate
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : update_hold
			always @ ( posedge clk or negedge rst_n ) begin
				if ( !rst_n )
					cnt[i] <= 0;
				else if (event_in_r[i] != event_in[i])
					cnt[i] <= 0;
				else if (cnt[i] != HOLD_CLKS - 1)
					cnt[i] <= cnt[i] + 1'b1;
			end
		end
	endgenerate
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : update_check
			always @ ( posedge clk or negedge rst_n ) begin
				if ( !rst_n )
					update[i] <= 1'b0;
				else if (event_in_r[i] != event_in[i])
					update[i] <= 1'b1;
				else if (cnt[i] == HOLD_CLKS - 1)
					update[i] <= 1'b0;
			end
		end
	endgenerate

	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			n <= 0;
		else if (n < CHIPSET_QTY-1)
			n <= n + 1'b1;
		else
			n  <= 0;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n )
			event_r <= 0;
		else if (update[n])
			event_r <= event_in[n];
	end
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
			assign event_in[i]	= event_in_arrary[32*i+31 : 32*i];
		end
	endgenerate
	
	assign event_out = event_r;
	
endmodule