`timescale 1ns/1ps
 
module sine_gen_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	parameter 		T_CLK 		= 10;		//ns
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg							clk					;
	reg							rst_n				;
	
	reg							enable_timer		;
	reg		[32-1:0]			update_period		;
	
	wire						trans_round			;
	wire						trans_pulse			;

	reg							aclken				;
	reg							areset				;
	wire						aresetn				;
	
	reg							phase_enable		;
	reg		[32-1:0]			phase_inc[0:16-1]	;
	reg		[32-1:0]			phase_off[0:16-1]	;
	
	wire	[32*16-1:0]			phase_inc_array		;
	wire	[32*16-1:0]			phase_off_array		;
	
	wire	[ 9*16-1:0]			sine_wave_array		;
	wire	[ 9-1:0]			wave_data[0:16-1]	;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	trans_timer u_trans_timer
		(
			.clk				( clk 				),
			.rst_n				( rst_n 			),
			
			.enable				( enable_timer 		),
			.update_period		( update_period		),
			
			.update				( trans_round   	),
			.trans				( trans_pulse   	)
		);
	
	sine_gen DUT
		(
			.clk				( clk				),
			.rst_n				( rst_n				),
			
			.aclken				( aclken			),
			.aresetn			( aresetn			),
			
			.phase_enable		( phase_enable		),
			.phase_inc_array	( phase_inc_array	),
			.phase_off_array	( phase_off_array	),
			
			.update				( trans_round		),
			.sine_wave_array	( sine_wave_array	)
		);
	
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		
		//aclken
		#600_000;
		@ ( posedge clk ) aclken <= 1'b1;
		#600_000;
		@ ( posedge clk ) aclken <= 1'b0;
		
		//aclken
		#600_000;
		@ ( posedge clk ) aclken <= 1'b1;
		#600_000;
		@ ( posedge clk ) aclken <= 1'b0;
		
		//areset
		#600_000;
		@ ( posedge clk ) areset <= 1'b1;
		#600_000;
		@ ( posedge clk ) areset <= 1'b0;
		
		//aclken
		#600_000;
		@ ( posedge clk ) aclken <= 1'b1;
		
		//areset
		#600_000;
		@ ( posedge clk ) areset <= 1'b1;
		
		//areset
		#600_000;
		@ ( posedge clk ) areset <= 1'b0;
		
		//aclken and areset
		#600_000;
		@ ( posedge clk ) aclken <= 1'b0;
		
		#600_000;
		@ ( posedge clk )
		phase_inc[ 0] = 32'h000A7C5B;
		phase_inc[ 1] = 32'h000FBA88;
		phase_inc[ 2] = 32'h0014F8B5;
		phase_inc[ 3] = 32'h001A36E3;
		phase_inc[ 4] = 32'h001F7510;
		phase_inc[ 5] = 32'h0024B33E;
		phase_inc[ 6] = 32'h0029F16B;
		phase_inc[ 7] = 32'h002F2F98;
		phase_inc[ 8] = 32'h003F2F98;
		phase_inc[ 9] = 32'h004F2F98;
		phase_inc[10] = 32'h005F2F98;
		phase_inc[11] = 32'h006F2F98;
		phase_inc[12] = 32'h007F2F98;
		phase_inc[13] = 32'h008F2F98;
		phase_inc[14] = 32'h009F2F98;
		phase_inc[15] = 32'h00AF2F98;
		@ ( posedge clk ) phase_enable <= 1'b1;
		@ ( posedge clk ) phase_enable <= 1'b0;
		
		//aclken and areset
		#600_000;
		@ ( posedge clk ) areset <= 1'b0;
		@ ( posedge clk ) aclken <= 1'b1;
		
		//aclken and areset
		#600_000;
		@ ( posedge clk ) aclken <= 1'b0;
		@ ( posedge clk ) areset <= 1'b1;

		#600_000;
		@ ( posedge clk )
		phase_inc[ 0] = 32'h000A7C5B;
		phase_inc[ 1] = 32'h000FBA88;
		phase_inc[ 2] = 32'h0014F8B5;
		phase_inc[ 3] = 32'h001A36E3;
		phase_inc[ 4] = 32'h001F7510;
		phase_inc[ 5] = 32'h0024B33E;
		phase_inc[ 6] = 32'h0029F16B;
		phase_inc[ 7] = 32'h002F2F98;
		phase_inc[ 8] = 32'h003F2F98;
		phase_inc[ 9] = 32'h004F2F98;
		phase_inc[10] = 32'h005F2F98;
		phase_inc[11] = 32'h006F2F98;
		phase_inc[12] = 32'h007F2F98;
		phase_inc[13] = 32'h008F2F98;
		phase_inc[14] = 32'h009F2F98;
		phase_inc[15] = 32'h00AF2F98;
		@ ( posedge clk ) phase_enable <= 1'b1;
		@ ( posedge clk ) phase_enable <= 1'b0;
		
		//aclken and areset
		#600_000;
		@ ( posedge clk ) aclken <= 1'b1;
		@ ( posedge clk ) areset <= 1'b0;
		
		//aclken and areset
		#600_000;
		@ ( posedge clk ) aclken <= 1'b1;
		@ ( posedge clk ) areset <= 1'b1;

		#600_000;
		@ ( posedge clk )
		phase_inc[ 0] = 32'h000A7C5B;
		phase_inc[ 1] = 32'h000FBA88;
		phase_inc[ 2] = 32'h0014F8B5;
		phase_inc[ 3] = 32'h001A36E3;
		phase_inc[ 4] = 32'h001F7510;
		phase_inc[ 5] = 32'h0024B33E;
		phase_inc[ 6] = 32'h0029F16B;
		phase_inc[ 7] = 32'h002F2F98;
		phase_inc[ 8] = 32'h003F2F98;
		phase_inc[ 9] = 32'h004F2F98;
		phase_inc[10] = 32'h005F2F98;
		phase_inc[11] = 32'h006F2F98;
		phase_inc[12] = 32'h007F2F98;
		phase_inc[13] = 32'h008F2F98;
		phase_inc[14] = 32'h009F2F98;
		phase_inc[15] = 32'h00AF2F98;
		@ ( posedge clk ) phase_enable <= 1'b1;
		@ ( posedge clk ) phase_enable <= 1'b0;
		
		//aclken and areset
		#600_000;
		@ ( posedge clk ) areset <= 1'b0;

		#600_000;
		@ ( posedge clk )
		phase_inc[ 0] = 32'h000A7C5B;
		phase_inc[ 1] = 32'h000FBA88;
		phase_inc[ 2] = 32'h0014F8B5;
		phase_inc[ 3] = 32'h001A36E3;
		phase_inc[ 4] = 32'h001F7510;
		phase_inc[ 5] = 32'h0024B33E;
		phase_inc[ 6] = 32'h0029F16B;
		phase_inc[ 7] = 32'h002F2F98;
		phase_inc[ 8] = 32'h003F2F98;
		phase_inc[ 9] = 32'h004F2F98;
		phase_inc[10] = 32'h005F2F98;
		phase_inc[11] = 32'h006F2F98;
		phase_inc[12] = 32'h007F2F98;
		phase_inc[13] = 32'h008F2F98;
		phase_inc[14] = 32'h009F2F98;
		phase_inc[15] = 32'h00AF2F98;
		@ ( posedge clk ) phase_enable <= 1'b1;
		@ ( posedge clk ) phase_enable <= 1'b0;

		#4_000_000;
		@ ( posedge clk ) aclken <= 1'b0;
		@ ( posedge clk ) areset <= 1'b1;

		#600_000;
		@ ( posedge clk ) aclken <= 1'b1;
		@ ( posedge clk ) areset <= 1'b0;

		#3_900_000;
		@ ( posedge clk ) areset <= 1'b1;

		#600_000;
		@ ( posedge clk ) areset <= 1'b0;

		#10_000_000;
		$stop;
		
		#600_000;
		@ ( posedge clk ) enable_timer <= 1'b1;
		
		#600_000;
		$stop;

	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk				<= 1'b0		;
			rst_n			<= 1'b0		;
			
			enable_timer	<= 1'b0		;
			update_period	<= 5_000/10	;	//30_000 ns
			
			aclken			<= 1'b0		;
			areset			<= 1'b0		;
			
			phase_enable	<= 8'd0		;
			
			phase_inc[ 0] = 32'h00000000;
			phase_inc[ 1] = 32'h00000000;
			phase_inc[ 2] = 32'h00000000;
			phase_inc[ 3] = 32'h00000000;
			phase_inc[ 4] = 32'h00000000;
			phase_inc[ 5] = 32'h00000000;
			phase_inc[ 6] = 32'h00000000;
			phase_inc[ 7] = 32'h00000000;
			phase_inc[ 8] = 32'h00000000;
			phase_inc[ 9] = 32'h00000000;
			phase_inc[10] = 32'h00000000;
			phase_inc[11] = 32'h00000000;
			phase_inc[12] = 32'h00000000;
			phase_inc[13] = 32'h00000000;
			phase_inc[14] = 32'h00000000;
			phase_inc[15] = 32'h00000000;
		
			phase_off[ 0] = 32'h00000000;
			phase_off[ 1] = 32'h00100000;
			phase_off[ 2] = 32'h00200000;
			phase_off[ 3] = 32'h00300000;
			phase_off[ 4] = 32'h00400000;
			phase_off[ 5] = 32'h00500000;
			phase_off[ 6] = 32'h00600000;
			phase_off[ 7] = 32'h00700000;
			phase_off[ 8] = 32'h00800000;
			phase_off[ 9] = 32'h00900000;
			phase_off[10] = 32'h00A00000;
			phase_off[11] = 32'h00B00000;
			phase_off[12] = 32'h00C00000;
			phase_off[13] = 32'h00D00000;
			phase_off[14] = 32'h00E00000;
			phase_off[15] = 32'h00F00000;
			
		end
	endtask	
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	assign aresetn = ~areset;

	genvar i;
	
	generate
		for(i=0;i<16;i=i+1) begin : pack
			assign phase_inc_array[32*i+31 : 32*i] = phase_inc[i];
			assign phase_off_array[32*i+31 : 32*i] = phase_off[i];
		end
	endgenerate
	
	generate
		for(i=0;i<16;i=i+1) begin : unpack
			assign wave_data[i] = sine_wave_array[9*i+8 : 9*i];
		end
	endgenerate
	
	
endmodule