`timescale 1ns/1ps
 
module rhs2116_top_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	parameter	T_CLK 			= 10;		//ns
	parameter	CHIPSET_QTY		=  4;
	
	parameter	RECORD_DIVISOR		=  2-1;

	parameter	CMD_CNV				= 2'b00;
	parameter	CMD_EXTEND			= 2'b01;
	parameter	CMD_STIM			= 2'b01;
	parameter	CMD_NULL			= 2'b01;
	parameter	CMD_END				= 2'b01;
	parameter	CMD_WRITE			= 2'b10;
	parameter	CMD_READ			= 2'b11;
	
	parameter	STIM_MONITOR_REG_ADDR	= 8'd40;
	parameter	STIM_POLARITY_REG_ADDR	= 8'd44;
	parameter	POS_CUR_REG_ADDR		= 8'd96;
	parameter	NEG_CUR_REG_ADDR		= 8'd64;
	
	
	localparam 	BRAM_ADDR_TEST_RW				= 13'h0000;
	localparam 	BRAM_ADDR_TEST_RO_DATA			= 13'h0004;
	localparam 	BRAM_ADDR_TEST_VERSION			= 13'h0008;
	
	localparam 	BRAM_ADDR_UPDATE_PERIOD			= 13'h0020;
	localparam 	BRAM_ADDR_UPLOAD_ROUND_NUM		= 13'h0024;
	localparam 	BRAM_ADDR_ENABLE				= 13'h0028;
	localparam 	BRAM_ADDR_RESET					= 13'h002C;
	localparam 	BRAM_ADDR_DDS_PHASE_TRIG		= 13'h0030;
	localparam	BRAM_ADDR_UPLOAD_TIMEOUT		= 13'h0048;
	
	localparam 	BRAM_ADDR_SPI_STATE_START		= 13'h0100;
	localparam 	BRAM_ADDR_SPI_TX_START			= 13'h0180;
	localparam 	BRAM_ADDR_SPI_RX_START			= 13'h0200;
	localparam 	BRAM_ADDR_SPI_ERR_START			= 13'h0280;
	
	
	localparam 	BRAM_ADDR_DDS_PHASE_INC_START	= 13'h0400;
	localparam 	BRAM_ADDR_DDS_PHASE_OFF_START	= 13'h0480;
	
	localparam 	BRAM_ADDR_CHIP_0_CNV_CMD_LTH	= 13'h0500;
	localparam 	BRAM_ADDR_CHIP_1_CNV_CMD_LTH	= 13'h0504;
	localparam 	BRAM_ADDR_CHIP_2_CNV_CMD_LTH	= 13'h0508;
	localparam 	BRAM_ADDR_CHIP_3_CNV_CMD_LTH	= 13'h050C;
	
	localparam 	BRAM_ADDR_STIM_TRIM_P_MASK		= 13'h1F00;
	localparam 	BRAM_ADDR_STIM_TRIM_P_START		= 13'h0600;
	
	localparam 	BRAM_ADDR_STIM_TRIM_N_MASK		= 13'h1F00;
	localparam 	BRAM_ADDR_STIM_TRIM_N_START		= 13'h0700;
	
	localparam 	BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_P	= 13'h0600;
	localparam 	BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_P	= 13'h0610;
	localparam 	BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_P	= 13'h0620;
	localparam 	BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_P	= 13'h0630;
	
	localparam 	BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_N	= 13'h0700;
	localparam 	BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_N	= 13'h0710;
	localparam 	BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_N	= 13'h0720;
	localparam 	BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_N	= 13'h0730;
	
	localparam 	BRAM_ADDR_CHIP_0_CNV_CMD_START	= 13'h1000;
	localparam 	BRAM_ADDR_CHIP_1_CNV_CMD_START	= 13'h1040;
	localparam 	BRAM_ADDR_CHIP_2_CNV_CMD_START	= 13'h1080;
	localparam 	BRAM_ADDR_CHIP_3_CNV_CMD_START	= 13'h10C0;
	
	localparam 	CHIP_0	= 4'h0;
	localparam 	CHIP_1	= 4'h1;
	localparam 	CHIP_2	= 4'h2;
	localparam 	CHIP_3	= 4'h3;
	
	localparam 	CHANNEL_0	= 0;
	localparam 	CHANNEL_1	= 1;
	localparam 	CHANNEL_2	= 2;
	localparam 	CHANNEL_3	= 3;
	localparam 	CHANNEL_4	= 4;
	localparam 	CHANNEL_5	= 5;
	localparam 	CHANNEL_6	= 6;
	localparam 	CHANNEL_7	= 7;
	localparam 	CHANNEL_8	= 8;
	localparam 	CHANNEL_9	= 9;
	localparam 	CHANNEL_A	= 10;
	localparam 	CHANNEL_B	= 11;
	localparam 	CHANNEL_C	= 12;
	localparam 	CHANNEL_D	= 13;
	localparam 	CHANNEL_E	= 14;
	localparam 	CHANNEL_F	= 15;
	
	localparam 	DDS_CH_0	= 0;
	localparam 	DDS_CH_1	= 1;
	localparam 	DDS_CH_2	= 2;
	localparam 	DDS_CH_3	= 3;
	localparam 	DDS_CH_4	= 4;
	localparam 	DDS_CH_5	= 5;
	localparam 	DDS_CH_6	= 6;
	localparam 	DDS_CH_7	= 7;
	localparam 	DDS_CH_8	= 8;
	localparam 	DDS_CH_9	= 9;
	localparam 	DDS_CH_A	= 10;
	localparam 	DDS_CH_B	= 11;
	localparam 	DDS_CH_C	= 12;
	localparam 	DDS_CH_D	= 13;
	localparam 	DDS_CH_E	= 14;
	localparam 	DDS_CH_F	= 15;
	
	localparam 	GAIN_MAX	= 9'h100;

	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg								clk					;
	reg								rst_n				;
	
	reg		[31:0]					temp				;
	
	reg		[13-1:0]				bram_addr			;
//	reg								bram_clk			;
	reg		[32-1:0]				bram_din			;
	wire	[32-1:0]				bram_dout			;
	reg								bram_en				;
	reg								bram_rst			;
	reg		[ 4-1:0]				bram_we				;
	
	wire							interrupt			;
	wire	[31:0]					stim_event_code		;

	//------------------------------------------ FIFO: stim input
	wire		[31:0]				axi_str_txd_tdata	;
	wire							axi_str_txd_tlast	;
	wire							axi_str_txd_tready	;
	wire							axi_str_txd_tvalid	;
	
	//------------------------------------------ FIFO: record output
	wire	[31:0]					axi_str_rxd_tdata	;
	wire							axi_str_rxd_tlast	;
	reg								axi_str_rxd_tready	;
	wire							axi_str_rxd_tvalid	;

	//------------------------------------------ device spi
	wire	[CHIPSET_QTY-1:0]		cs					;
	wire	[CHIPSET_QTY-1:0]		sclk				;
	wire	[CHIPSET_QTY-1:0]		mosi				;
	wire	[CHIPSET_QTY-1:0]		miso				;
	
	reg		[31:0]					s_axis_tdata		;
	reg								s_axis_tlast		;
	wire							s_axis_tready		;
	reg								s_axis_tvalid		;
	
	wire	[31:0]					axis_tdata_1		;
	wire							axis_tlast_1		;
	wire							axis_tready_1		;
	wire							axis_tvalid_1		;
	
	wire	[31:0]					axis_tdata_2		;
	wire							axis_tlast_2		;
	wire							axis_tready_2		;
	wire							axis_tvalid_2		;

	reg								no_enable			;
	
	integer n;
	reg [3:0] chip;
	genvar	i;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	axis_data_fifo_w32_d32 u_axis_stream_data_fifo_1
		(
			.s_axis_aclk		( clk 				),
			.s_axis_aresetn		( rst_n				),
			
			.s_axis_tvalid		( s_axis_tvalid		),
			.s_axis_tready		( s_axis_tready		),
			.s_axis_tdata		( s_axis_tdata  	),
			.s_axis_tlast		( s_axis_tlast 		),
			
			.m_axis_tvalid		( axis_tvalid_1		),
			.m_axis_tready		( axis_tready_1   	),
			.m_axis_tdata		( axis_tdata_1   	),
			.m_axis_tlast		( axis_tlast_1   	)
		);
		
	axis_data_fifo_w32_d32 u_axis_stream_data_fifo_2
		(
			.s_axis_aclk		( clk 				),
			.s_axis_aresetn		( rst_n				),
			
			.s_axis_tvalid		( axis_tvalid_1		),
			.s_axis_tready		( axis_tready_1		),
			.s_axis_tdata		( axis_tdata_1  	),
			.s_axis_tlast		( axis_tlast_1 		),
			
			.m_axis_tvalid		( axis_tvalid_2		),
			.m_axis_tready		( axis_tready_2   	),
			.m_axis_tdata		( axis_tdata_2   	),
			.m_axis_tlast		( axis_tlast_2   	)
		);
		
	axis_data_fifo_w32_d32 u_axis_stream_data_fifo_3
		(
			.s_axis_aclk		( clk 				),
			.s_axis_aresetn		( rst_n				),
			
			.s_axis_tvalid		( axis_tvalid_2		),
			.s_axis_tready		( axis_tready_2		),
			.s_axis_tdata		( axis_tdata_2  	),
			.s_axis_tlast		( axis_tlast_2 		),
			
			.m_axis_tvalid		( axi_str_txd_tvalid	),
			.m_axis_tready		( axi_str_txd_tready   	),
			.m_axis_tdata		( axi_str_txd_tdata   	),
			.m_axis_tlast		( axi_str_txd_tlast   	)
		);
		
	rhs2116_top# 
		(
			.CLK_PERIOD			( T_CLK				),
			.VERSION			( 32'h1000000		),
			.CHIPSET_QTY		( CHIPSET_QTY		),
			.SPI_CLK_DIV		( 4					),
			.SPI_TRANS_PERIOD	( 1500				)
		)
	DUT
		(
			.clk				( clk				),
			.rst_n				( rst_n				),
			
			.bram_addr			( bram_addr			),
			.bram_clk			( 1'b0				),
			.bram_din			( bram_din			),
			.bram_dout			( bram_dout			),
			.bram_en			( bram_en			),
			.bram_rst			( bram_rst			),
			.bram_we			( bram_we			),
			
			.interrupt			( interrupt			),
			.stim_event_code	( stim_event_code	),
			
			//------------------------------------------ FIFO: stim input and record output
			.axi_str_txd_tdata	( axi_str_txd_tdata	),
			.axi_str_txd_tlast	( 1'b0				),
			.axi_str_txd_tready	( axi_str_txd_tready),
			.axi_str_txd_tvalid	( axi_str_txd_tvalid),
			
			.axi_str_rxd_tdata	( axi_str_rxd_tdata	),
			.axi_str_rxd_tlast	( axi_str_rxd_tlast	),
			.axi_str_rxd_tready	( axi_str_rxd_tready),
			.axi_str_rxd_tvalid	( axi_str_rxd_tvalid),

			//------------------------------------------ channel stim state
			.sw_enable			( 					),
			.sw_data_sel		( 					),
			.sw_data_0			( 					),
			.sw_data_1			( 					),
			.sw_state			( 32'h00000000		),
			
			//------------------------------------------ device spi
			.stim_en			( 					),
			.cs					( cs				),
			.sclk				( sclk				),
			.mosi				( mosi				),
			.miso				( miso				),

			.debug_sig			(					)
		);
	
	generate
		for(i=0; i<CHIPSET_QTY; i=i+1) begin : spi
			rhs2116_mod u_rhs2116_mod
				(
					.cs		( cs[i]		),
					.sclk	( sclk[i]	),
					.mosi	( mosi[i]	),
					.miso	( miso[i]	)
				);
		end
	endgenerate
	
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		#100
		
		//Config DDS
		write_bram(BRAM_ADDR_DDS_PHASE_INC_START + 8'h00, 32'h000029F1);
		write_bram(BRAM_ADDR_DDS_PHASE_OFF_START, 32'h0);
		write_bram(BRAM_ADDR_DDS_PHASE_TRIG, 1);
		
		//Config update period
		write_bram(BRAM_ADDR_UPDATE_PERIOD, 10000/T_CLK);
		write_bram(BRAM_ADDR_UPLOAD_ROUND_NUM, 10);
		write_bram(BRAM_ADDR_UPLOAD_TIMEOUT, 70);
		
		#100
		@ ( posedge clk );
		while(1) begin
			write_fifo(code_stim_sine(CHIP_0, CHANNEL_0, DDS_CH_0, GAIN_MAX),	1'b0);
			write_fifo(code_stim_sine(CHIP_0, CHANNEL_1, DDS_CH_0, GAIN_MAX),	1'b0);
			write_fifo(code_write_u  (CHIP_0, STIM_POLARITY_REG_ADDR, 16'h00),	1'b0);
			write_fifo(code_read	 (CHIP_0, STIM_MONITOR_REG_ADDR),			1'b0);

			write_fifo(code_cnv		 (CHIP_1, CHANNEL_0),						1'b0);
			write_fifo(code_cnv		 (CHIP_1, CHANNEL_1),						1'b0);
			write_fifo(code_read	 (CHIP_1, 8'hFB),							1'b0);
			write_fifo(code_read	 (CHIP_1, 8'hFC),							1'b0);

			write_fifo(code_stim_sine(CHIP_2, CHANNEL_0, DDS_CH_0, GAIN_MAX),	1'b0);
			write_fifo(code_cnv		 (CHIP_2, CHANNEL_1),						1'b0);
			write_fifo(code_write_u  (CHIP_2, STIM_POLARITY_REG_ADDR, 16'h00),	1'b0);
			write_fifo(code_read	 (CHIP_2, STIM_MONITOR_REG_ADDR),			1'b0);

			write_fifo(code_null	 (CHIP_3),									1'b0);
			write_fifo(code_null	 (CHIP_3),									1'b0);
			write_fifo(code_null	 (CHIP_3),									1'b0);
			write_fifo(code_null	 (CHIP_3),									1'b0);

			write_fifo(code_end		 (0),										1'b1);

			@ ( posedge clk );
			if (no_enable) begin
				no_enable <= 1'b0;
				write_bram(BRAM_ADDR_ENABLE, 32'hF);
			end
		end
		
		$stop;
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk			<= 1'b0	;
			rst_n		<= 1'b0	;
			

			bram_addr	<= 0	;
			bram_din	<= 0	;
			bram_en		<= 0	;
			bram_rst	<= 0	;
			bram_we		<= 0	;

			s_axis_tdata	<= 0	;
			s_axis_tlast	<= 1'b0	;
			s_axis_tvalid	<= 1'b0	;
		
			axi_str_rxd_tready <= 1'b1;

			no_enable		<= 1'b1;
		end
	endtask
	
	task write_bram;
		input [12:0] addr;
		input [31:0] data;
		begin
			@ ( posedge clk );
			bram_addr	<= addr;
			bram_din	<= data;
			bram_en		<= 1;
			bram_we		<= 4'hF	;
			@ ( posedge clk );
			bram_en		<= 0;
			bram_we		<= 4'h0;
		end
	endtask
	
	task read_bram;
		input [12:0] addr;
		output [31:0] data;
		begin
			@ ( posedge clk );
			bram_addr	<= addr;
			bram_en		<= 1;
			bram_we		<= 4'h0	;
			@ ( posedge clk );
			bram_en		<= 0;
			@ ( posedge clk );
			data <= bram_dout;
		end
	endtask
	
	task write_fifo;
		input [32-1:0]	tdata;
		input			tlast;
		begin
			s_axis_tdata	<= tdata;
			s_axis_tvalid	<= 1'b1;
			s_axis_tlast	<= tlast;
			@ ( posedge clk );
			while(~s_axis_tready) @ ( posedge clk );
			if(tlast) begin
				s_axis_tvalid	<= 1'b0;
				s_axis_tlast	<= 1'b0;
			end
		end
	endtask

	function [32:0] code_null;
		input [4-1:0]	chip;
		code_null = {CMD_NULL, 2'b00, chip, 24'd0};
	endfunction

	function [32:0] code_cnv;
		input [4-1:0]	chip;
		input [6-1:0]	channel;
		code_cnv = {CMD_CNV, 4'd0, chip, channel, 16'd0};
	endfunction

	function [32:0] code_stim_sine;
		input [4-1:0]	chip;
		input [4-1:0]	channel;
		input [7-1:0]	dds_ch;
		input [9-1:0]	gain;
		code_stim_sine = {CMD_STIM, 2'b00, chip, 4'h1, channel, dds_ch, gain};
	endfunction

	function [32:0] code_stim_sine_cover_cnv;
		input [4-1:0]	chip;
		input [4-1:0]	channel;
		input [7-1:0]	dds_ch;
		input [9-1:0]	gain;
		code_stim_sine_cover_cnv = {CMD_STIM, 2'b00, chip, 4'h2, channel, dds_ch, gain};
	endfunction

	function [32:0] code_write;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		input [16-1:0]	data;
		code_write = {CMD_WRITE, 2'b00, chip, reg_addr, data};
	endfunction

	function [32:0] code_write_u;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		input [16-1:0]	data;
		code_write_u = {CMD_WRITE, 2'b10, chip, reg_addr, data};
	endfunction

	function [32:0] code_read;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		code_read = {CMD_READ, 2'b00, chip, reg_addr, 16'd0};
	endfunction

	function [32:0] code_read_u;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		code_read_u = {CMD_READ, 2'b10, chip, reg_addr, 16'd0};
	endfunction

	function [32:0] code_end;
		input [16-1:0]	data;
		code_end = {CMD_END, 6'd0, 8'hF0, data};
	endfunction
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	//
	
endmodule