`timescale 1 ns / 1 ps

module rhs2116_top#
	(
		parameter 		VERSION 			= 32'h10000000	,
		parameter		CLK_PERIOD			= 10			,

		parameter 		SPI_CLK_DIV			= 4				,
		parameter 		SPI_DATA_WIDTH		= 32			,
		parameter		SPI_TRANS_PERIOD	= 1500			,	//Unit: ns

		parameter		CHIPSET_QTY			= 4				,
		parameter		CH_OF_CHIPSET		= 16			,

		parameter 		REG_ADDR_STIM_POL	= 8'd44			,
		parameter 		REG_ADDR_POS_CUR	= 8'd96			,
		parameter 		REG_ADDR_NEG_CUR	= 8'd64
	)
	(
		input							clk					,
		input							rst_n				,
		
		input	[13-1:0]				bram_addr			,
		input							bram_clk			,
		input	[32-1:0]				bram_din			,
		output	[32-1:0]				bram_dout			,
		input							bram_en				,
		input							bram_rst			,
		input	[ 4-1:0]				bram_we				,
		
		output							interrupt			,
		
		//------------------------------------------ Trigger
		output	[32-1:0]				stim_event_code		,
	
		//------------------------------------------ FIFO: stim data input
		input	[32-1:0]				axi_str_txd_tdata	,
		input							axi_str_txd_tlast	,
		output							axi_str_txd_tready	,
		input							axi_str_txd_tvalid	,
		
		//------------------------------------------ FIFO: record data output
		output	[32-1:0]				axi_str_rxd_tdata	,
		output							axi_str_rxd_tlast	,
		input							axi_str_rxd_tready	,
		output							axi_str_rxd_tvalid	,

		//------------------------------------------ channel stim state
		output							sw_enable			,
		output							sw_data_sel			,
		output	[64-1:0]				sw_data_0			,
		output	[64-1:0]				sw_data_1			,
		input	[64-1:0]				sw_state			,
	
		//------------------------------------------ device
		output	[CHIPSET_QTY-1:0]		stim_en				,
		output	[CHIPSET_QTY-1:0]		cs					,
		output	[CHIPSET_QTY-1:0]		sclk				,
		output	[CHIPSET_QTY-1:0]		mosi				,
		input	[CHIPSET_QTY-1:0]		miso				,
		
		output	[ 4-1:0]				debug_sig
	);
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	//--------------------------------------------------------------------- config
	wire	[32-1:0]				update_period						;	
	
	wire							enable_timer						;
	wire							dds_by_ps							;
	
	wire							dds_aclken_ps						;
	wire							dds_aresetn_ps						;
	wire							dds_aclken_pl						;
	wire							dds_aresetn_pl						;
	
	wire							dds_aclken							;
	wire							dds_aresetn							;
	
	wire	[16* 8*CHIPSET_QTY-1:0]	stim_trim_p_array_array				;
	wire	[16* 8*CHIPSET_QTY-1:0]	stim_trim_n_array_array				;
	wire	[16* 8-1:0]				stim_trim_p_array[0:CHIPSET_QTY-1]	;
	wire	[16* 8-1:0]				stim_trim_n_array[0:CHIPSET_QTY-1]	;
	
	wire							phase_enable						;
	wire	[32*16-1:0]				phase_inc_array						;
	wire	[32*16-1:0]				phase_off_array						;
	
	wire	[16*9-1:0]				sine_wave_array						;
	
	//--------------------------------------------------------------------- spi communication
	wire	[ 1*CHIPSET_QTY-1:0]	spi_cmd_valid_array					;
	wire	[32*CHIPSET_QTY-1:0]	spi_cmd_data_array					;
	wire	[ 1*CHIPSET_QTY-1:0]	spi_cmd_ready_array					;
	wire	[ 1*CHIPSET_QTY-1:0]	spi_res_en_array					;
	wire	[32*CHIPSET_QTY-1:0]	spi_res_array						;
	
	wire							spi_cmd_valid[0:CHIPSET_QTY-1]		;
	wire	[32-1:0]				spi_cmd_data[0:CHIPSET_QTY-1]		;
	wire							spi_cmd_ready[0:CHIPSET_QTY-1]		;
	wire							spi_res_en[0:CHIPSET_QTY-1]			;
	wire	[32-1:0]				spi_res[0:CHIPSET_QTY-1]			;
	
	//--------------------------------------------------------------------- transmit timer
	wire							trans_round							;
	wire							trans_pulse							;
	
	//--------------------------------------------------------------------- stim stream
	wire	[32*CHIPSET_QTY-1:0]	axis_ctrl_tdata_array				;
	wire	[ 1*CHIPSET_QTY-1:0]	axis_ctrl_tlast_array				;
	wire	[ 1*CHIPSET_QTY-1:0]	axis_ctrl_tready_array				;
	wire	[ 1*CHIPSET_QTY-1:0]	axis_ctrl_tvalid_array				;
	
	wire	[32-1:0]				axis_ctrl_tdata[0:CHIPSET_QTY-1]	;
	wire							axis_ctrl_tlast[0:CHIPSET_QTY-1]	;
	wire							axis_ctrl_tready[0:CHIPSET_QTY-1]	;
	wire							axis_ctrl_tvalid[0:CHIPSET_QTY-1]	;

	wire	[16-1:0]				record_ch_qty						;
		
	wire	[32-1:0]				m_axi_trans_tdata[0:CHIPSET_QTY-1]	;
	wire							m_axi_trans_tlast[0:CHIPSET_QTY-1]	;
	wire							m_axi_trans_tready[0:CHIPSET_QTY-1]	;
	wire							m_axi_trans_tvalid[0:CHIPSET_QTY-1]	;
	
	//--------------------------------------------------------------------- conver result
	wire	[32-1:0]				cnv_res_tdata[0:CHIPSET_QTY-1]		;
	wire							cnv_res_tlast[0:CHIPSET_QTY-1]		;
	wire							cnv_res_tready[0:CHIPSET_QTY-1]		;
	wire							cnv_res_tvalid[0:CHIPSET_QTY-1]		;
	
	wire	[32*CHIPSET_QTY-1:0]	cnv_res_tdata_array					;
	wire	[   CHIPSET_QTY-1:0]	cnv_res_tlast_array					;
	wire	[   CHIPSET_QTY-1:0]	cnv_res_tready_array				;
	wire	[   CHIPSET_QTY-1:0]	cnv_res_tvalid_array				;
	
	//--------------------------------------------------------------------- Compliance Monitor
	wire	[            16-1:0]	monitor_data[0:CHIPSET_QTY-1]		;
	wire	[16*CHIPSET_QTY-1:0]	monitor_data_array					;
	wire	[            64-1:0]	stim_monitor_rt						;
	wire	[            64-1:0]	stim_monitor_latch					;

	wire	[			 16-1:0]	stim_state[0:CHIPSET_QTY-1]			;
	wire	[			 32-1:0]	stim_stage_code[0:CHIPSET_QTY-1]	;
	wire	[32*CHIPSET_QTY-1:0]	event_in_arrary						;
	
	genvar	i;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	transmit_config# 
		(
			.CHIPSET_QTY			( CHIPSET_QTY			)
		)
	u_transmit_config
		(
			.clk					( clk					),
			.rst_n					( rst_n					),
			
			.bram_addr				( bram_addr				),
			.bram_clk				( bram_clk				),
			.bram_din				( bram_din				),
			.bram_dout				( bram_dout				),
			.bram_en				( bram_en				),
			.bram_rst				( bram_rst				),
			.bram_we				( bram_we				),

			.stim_en				( stim_en				),
			
			.update_period			( update_period			),
			
			.enable_timer			( enable_timer			),

			.dds_by_ps				( dds_by_ps				),
			.dds_aclken				( dds_aclken_ps			),
			.dds_aresetn			( dds_aresetn_ps		),

			.sw_enable				( sw_enable				),
			.sw_data_sel			( sw_data_sel			),
			.sw_data_0				( sw_data_0				),
			.sw_state				( sw_state				),
			
			.stim_trim_p_array_array( stim_trim_p_array_array),
			.stim_trim_n_array_array( stim_trim_n_array_array),
			
			.phase_enable			( phase_enable			),
			.phase_inc_array		( phase_inc_array		),
			.phase_off_array		( phase_off_array		),
		
			.stim_monitor_rt		( stim_monitor_rt		),
			.stim_monitor_latch		( stim_monitor_latch	),
			
			.spi_cmd_valid_array	( spi_cmd_valid_array	),
			.spi_cmd_data_array		( spi_cmd_data_array	),
			.spi_cmd_ready_array	( spi_cmd_ready_array	),
			.spi_res_en_array		( spi_res_en_array		),
			.spi_res_array			( spi_res_array			)
		);
		
	trans_timer#
		(
			.CLK_PERIOD				( CLK_PERIOD			),
			.SPI_TRANS_PERIOD		( SPI_TRANS_PERIOD		)
		)
	u_trans_timer
		(
			.clk					( clk					),
			.rst_n					( rst_n					),
			
			.update_period			( update_period			),
			.enable					( axi_str_txd_tvalid	),	//enable_timer
			
			.trans_round			( trans_round			),
			.trans_pulse			( trans_pulse			)
		);
	
	sine_gen u_sine_wave_gen
		(
			.clk					( clk					),
			.rst_n					( rst_n					),
			
			.phase_enable			( phase_enable			),
			.phase_inc_array		( phase_inc_array		),
			.phase_off_array		( phase_off_array		),
			
			.dds_aclken				( dds_aclken			),
			.dds_aresetn			( dds_aresetn			),
			
			.update					( trans_round			),
			.sine_wave_array		( sine_wave_array		)
		);
	
	trans_distribute u_trans_distribute
		(
			.clk					( clk					),
			.rst_n					( rst_n					),

			.trans_round			( trans_round			), 
			
			.s_axi_rx_tdata			( axi_str_txd_tdata		),
			.s_axi_rx_tlast			( axi_str_txd_tlast		),
			.s_axi_rx_tready		( axi_str_txd_tready	),
			.s_axi_rx_tvalid		( axi_str_txd_tvalid	),

			.record_ch_qty			( record_ch_qty			),
			.dds_aclken				( dds_aclken_pl			),
			.dds_aresetn			( dds_aresetn_pl		),
			
			.m_axi_tx_aresetn		( rst_n					),
			.m_axi_tx_tdata_array	( axis_ctrl_tdata_array	),
			.m_axi_tx_tlast_array	( axis_ctrl_tlast_array	),
			.m_axi_tx_tready_array	( axis_ctrl_tready_array),
			.m_axi_tx_tvalid_array	( axis_ctrl_tvalid_array)
		);
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : transmit_arrange
			trans_arrange# 
				(
					.REG_ADDR_STIM_POL		( 8'd44					),
					.REG_ADDR_POS_CUR		( 8'd64					),
					.REG_ADDR_NEG_CUR		( 8'd96					)
				)
			u_trans_arrange
				(
					.clk					( clk					),
					.rst_n					( rst_n					),
					
					.stim_trim_p_array		( stim_trim_p_array[i]	),
					.stim_trim_n_array		( stim_trim_n_array[i]	),
					.sine_wave_array		( sine_wave_array		),
					
					.trans_round			( trans_round			), 
					
					//--------------------------------------------------input
					.s_axi_cmd_tdata		( axis_ctrl_tdata[i]	),
					.s_axi_cmd_tlast		( axis_ctrl_tlast[i]	),
					.s_axi_cmd_tready		( axis_ctrl_tready[i]	),
					.s_axi_cmd_tvalid		( axis_ctrl_tvalid[i]	),
					
					//--------------------------------------------------output
					.m_axi_trans_tdata		( m_axi_trans_tdata[i]	),
					.m_axi_trans_tlast		( m_axi_trans_tlast[i]	),
					.m_axi_trans_tready		( m_axi_trans_tready[i]	),
					.m_axi_trans_tvalid		( m_axi_trans_tvalid[i]	)
				);
		end
	endgenerate
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : trans_if
			transmit_if# 
				(
					.SPI_CLK_DIV			( SPI_CLK_DIV			),
					.SPI_DATA_WIDTH			( SPI_DATA_WIDTH		),
					.CH_OF_CHIPSET			( CH_OF_CHIPSET			),
					.CMD_CONVERT			( 2'b00					),
					.CMD_EXTEND				( 2'b01					),
					.CMD_WRITE				( 2'b10					),
					.CMD_READ				( 2'b11					),
					.REG_ADDR_MONITOR		( 8'd40					)
				)
			u_transmit_if
				(
					.clk					( clk					),
					.rst_n					( rst_n					),
					
					.trans_round			( trans_round			), 
					.trans_pulse			( trans_pulse			),
					
					//------------------------------------------ spi direct communication
					.spi_cmd_valid			( spi_cmd_valid[i]		),
					.spi_cmd_data			( spi_cmd_data[i]		),
					.spi_cmd_ready			( spi_cmd_ready[i]		),
					
					.spi_res_en				( spi_res_en[i]			),
					.spi_res				( spi_res[i]			),
					
					//------------------------------------------ cmd stream
					.s_axis_trans_tdata		( m_axi_trans_tdata[i]	),
					.s_axis_trans_tlast		( m_axi_trans_tlast[i]	),
					.s_axis_trans_tready	( m_axi_trans_tready[i]	),
					.s_axis_trans_tvalid	( m_axi_trans_tvalid[i]	),
					
					//------------------------------------------ record stream
					.cnv_res_tdata			( cnv_res_tdata[i]		),
					.cnv_res_tlast			( cnv_res_tlast[i]		),
					.cnv_res_tready			( cnv_res_tready[i]		),
					.cnv_res_tvalid			( cnv_res_tvalid[i]		),
					
					//------------------------------------------ monitor
					.monitor_data_en		( 						),
					.monitor_data			( monitor_data[i]		),

					.stim_state				( stim_state[i]			),
					.stim_stage_code		( stim_stage_code[i]	),
					
					//------------------------------------------ device spi
					.cs						( cs[i]					),
					.sclk					( sclk[i]				),
					.mosi					( mosi[i]				),
					.miso					( miso[i]				)
				);
		end
	endgenerate
	
	cnv_res_collect# 
		(
			.CHIPSET_QTY			( CHIPSET_QTY			),
			.CH_OF_CHIPSET			( CH_OF_CHIPSET			)
		)
	u_cnv_res_collect
		(
			.clk					( clk					),
			.rst_n					( rst_n					),

			.trans_round			( trans_round			),
			.record_ch_qty			( record_ch_qty			),
			
			.cnv_res_tdata_array	( cnv_res_tdata_array	),
			.cnv_res_tlast_array	( cnv_res_tlast_array	),
			.cnv_res_tready_array	( cnv_res_tready_array	),
			.cnv_res_tvalid_array	( cnv_res_tvalid_array	),
			
			.m_axis_eeg_tdata		( axi_str_rxd_tdata		),
			.m_axis_eeg_tlast		( axi_str_rxd_tlast		),
			.m_axis_eeg_tready		( axi_str_rxd_tready	),
			.m_axis_eeg_tvalid		( axi_str_rxd_tvalid	)
		);

	stim_event_collect#
		(
			.CHIPSET_QTY			( CHIPSET_QTY			)
		)
	u_stim_event_collect
		(
			.clk					( clk					),
			.rst_n					( rst_n					),

			.event_in_arrary		( event_in_arrary		),
			.event_out				( stim_event_code		)
		);

	stim_monitor#
		(
			.CLK_PERIOD				( CLK_PERIOD			)
		)
	u_stim_monitor
		(
			.clk					( clk					),
			.rst_n					( rst_n					),

			.stim_monitor_in		( monitor_data_array	),
			
			.stim_monitor_rt		( stim_monitor_rt		),
			.stim_monitor_latch		( stim_monitor_latch	)
		);
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	assign dds_aclken  = dds_by_ps? dds_aclken_ps :dds_aclken_pl;
	assign dds_aresetn = dds_by_ps? dds_aresetn_ps:dds_aresetn_pl;

	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack
			assign spi_cmd_ready_array[i]			= spi_cmd_ready[i];
			assign spi_res_en_array[i]				= spi_res_en[i];
			assign spi_res_array[32*i+31 : 32*i]	= spi_res[i];
			
			assign axis_ctrl_tready_array[i]		= axis_ctrl_tready[i];
			
			assign monitor_data_array[16*i+15 : 16*i]	= monitor_data[i];
			
			assign cnv_res_tdata_array[32*i+31 : 32*i] 	= cnv_res_tdata[i];
			assign cnv_res_tlast_array[i]				= cnv_res_tlast[i];
			assign cnv_res_tvalid_array[i]				= cnv_res_tvalid[i];

			assign sw_data_1[16*i+15 : 16*i]		= ~stim_state[i];

			assign event_in_arrary[32*i+31 : 32*i] 	= stim_stage_code[i];
		end
	endgenerate
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
			assign spi_cmd_data[i]	= spi_cmd_data_array[32*i+31 : 32*i];
			assign spi_cmd_valid[i]	= spi_cmd_valid_array[i];
			
			assign axis_ctrl_tdata[i]	= axis_ctrl_tdata_array[32*i+31 : 32*i];
			assign axis_ctrl_tlast[i]	= axis_ctrl_tlast_array[i];
			assign axis_ctrl_tvalid[i]	= axis_ctrl_tvalid_array[i];
			
			assign cnv_res_tready[i] = cnv_res_tready_array[i];
			
			assign stim_trim_p_array[i] = stim_trim_p_array_array[16*8*i+16*8-1: 16*8*i];
			assign stim_trim_n_array[i] = stim_trim_n_array_array[16*8*i+16*8-1: 16*8*i];
			
		end
	endgenerate

	assign interrupt = 1'b0;
	
	assign debug_sig[0] = cs[3];
	assign debug_sig[1] = sclk[3];
	assign debug_sig[2] = mosi[3];
	assign debug_sig[3] = miso[3];
	
endmodule