`timescale 1 ns / 1 ps

module record_config#
	(
		parameter	SPIS_QTY			= 4			    	,
		parameter	SPI_DATA_WIDTH		= 8
	)
	(
		input							clk					,
		input							rst_n				,
		
		input		[13-1:0]			bram_addr			,
		input							bram_clk			,
		input		[32-1:0]			bram_din			,
		output	reg	[32-1:0]			bram_dout			,
		input							bram_en				,
		input							bram_rst			,
		input		[ 4-1:0]			bram_we				,

		output		[32-1:0]			emg_cr				,
		input		[32-1:0]			emg_sr				,
		output		[32-1:0]			emg_tr				,
		input		[32-1:0]			emg_rr				,

		output	reg						emg_sr_r_evt
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	BRAM_ADDR_TEST_RO				= 13'h0000;
	localparam 	BRAM_ADDR_TEST_RW				= 13'h0004;
	
	localparam 	BRAM_ADDR_EMG_CR				= 13'h0020;
	localparam 	BRAM_ADDR_EMG_SR				= 13'h0024;
	localparam 	BRAM_ADDR_EMG_TR				= 13'h0028;
	localparam 	BRAM_ADDR_EMG_RR				= 13'h002C;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg		[32-1:0]		test_data						;
	
	wire					bram_wr_valid					;
	wire					bram_rd_valid					;

	reg		[32-1:0]		emg_cr_r						;
	reg		[32-1:0]		emg_tr_r						;
	
	integer	n;
	
	genvar i;
	
	//*****************************************************************************
	// Procedural blocks
	//*****************************************************************************

	//write bram/Set config
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			test_data <= 0;
		else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_TEST_RW ) )
			test_data <= bram_din;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			emg_cr_r <= 0;
		end else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_EMG_CR ) ) begin
			emg_cr_r <= bram_din;
		end else begin
			emg_cr_r <= 0;
		end
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			emg_tr_r <= 0;
		else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_EMG_TR ) )
			emg_tr_r <= bram_din;
	end
	
	//read bram/Get config
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			bram_dout <= 0;
		end else if ( bram_rd_valid ) begin
			
			if ( bram_addr  == BRAM_ADDR_TEST_RO )
				bram_dout <= 32'h12345678;
			
			if ( bram_addr  == BRAM_ADDR_EMG_SR )
				bram_dout <= emg_sr;
			
			if ( bram_addr  == BRAM_ADDR_EMG_RR )
				bram_dout <= emg_rr;
			
		end
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			emg_sr_r_evt <= 1'b0;
		else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_EMG_SR ) )
			emg_sr_r_evt <= 1'b1;
		else
			emg_sr_r_evt <= 1'b0;
	end
	
	//*****************************************************************************
	// Continuous assignments
	//*****************************************************************************
	assign bram_wr_valid = bram_en && (bram_we == 4'hF);
	assign bram_rd_valid = bram_en && (bram_we == 4'h0);

	assign emg_cr = emg_cr_r;
	assign emg_tr = emg_tr_r;
	
endmodule