`timescale 1 ns / 1 ps

module accel_top#
	(
		parameter						CLK_PERIOD		= 10
	)
	(
		input							clk					,
		input							rst_n				,
		
		input	[13-1:0]				bram_addr			,
		input							bram_clk			,
		input	[32-1:0]				bram_din			,
		output	[32-1:0]				bram_dout			,
		input							bram_en				,
		input							bram_rst			,
		input	[ 4-1:0]				bram_we				,

		output							interrupt			,
		output	[16*3-1:0]				accel_data			,
		
		output							accel_spi_cs		,
		output							accel_spi_sclk		,
		output							accel_spi_mosi		,
		input							accel_spi_miso		,
		input							accel_int0			,
		input							accel_int1
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	// wire						stream_enable			;

	// wire    [ 8-1:0]			t_tdata					;
    // wire						t_tready				;
    // wire						t_tvalid				;
	
	// wire    [ 8-1:0]			t_tdata_ps				;
    // wire						t_tready_ps				;
    // wire						t_tvalid_ps				;
	
	// wire    [ 8-1:0]			t_tdata_pl				;
    // wire						t_tready_pl				;
    // wire						t_tvalid_pl				;
    
	// wire    [ 8-1:0]			r_tdata					;
    // wire						r_tvalid				;

	// wire    [ 8-1:0]			r_tdata_ps				;
    // wire						r_tvalid_ps				;

	// wire    [ 8-1:0]			r_tdata_pl				;
    // wire						r_tvalid_pl				;

	// wire	[16-1:0]			out_x					;
	// wire	[16-1:0]			out_y					;
	// wire	[16-1:0]			out_z					;

	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	// accel_config# 
	// 	(
	// 		.SPI_DATA_WIDTH		( 8						)
	// 	)
	// u_accel_config
	// 	(
	// 		.clk				( clk					),
	// 		.rst_n				( rst_n					),
			
	// 		.bram_addr			( bram_addr				),
	// 		.bram_clk			( bram_clk				),
	// 		.bram_din			( bram_din				),
	// 		.bram_dout			( bram_dout				),
	// 		.bram_en			( bram_en				),
	// 		.bram_rst			( bram_rst				),
	// 		.bram_we			( bram_we				),
			
	// 		.t_tdata			( t_tdata_ps			),
	// 		.t_tready			( t_tready_ps			),
	// 		.t_tvalid			( t_tvalid_ps			),

	// 		.r_tdata			( r_tdata_ps			),
	// 		.r_tvalid			( r_tvalid_ps			),

	// 		.stream_enable		( stream_enable			)
	// 	);

	// accel_stream# 
	// 	(
	// 		.CLK_PERIOD			( 10					),
	// 		.SPI_DATA_WIDTH		( 8						)
	// 	)
	// u_accel_stream
	// 	(
	// 		.clk				( clk					),
	// 		.rst_n				( rst_n					),

	// 		.enable				( stream_enable			),
	// 		.accel_int			( accel_int0				),
			
	// 		.t_tdata			( t_tdata_ps			),
	// 		.t_tready			( t_tready_ps			),
	// 		.t_tvalid			( t_tvalid_ps			),

	// 		.r_tdata			( r_tdata_ps			),
	// 		.r_tvalid			( r_tvalid_ps			),

	// 		.out_x				( out_x					),
	// 		.out_y				( out_y					),
	// 		.out_z				( out_z					)
	// 	);
	
    // lis2dw12_spi# 
    //     (
    //         .CLK_PERIOD			( 10					),
    //         .CLK_DIV			( 10					),
    //         .DATA_WIDTH			( 8						)
    //     )
    // u_lis2dw12_spi
    //     (
    //         .clk				( clk 					),
    //         .rst_n				( rst_n 				),
            
    //         .t_tdata			( t_tdata 		    	),
    //         .t_tready			( t_tready		    	),
    //         .t_tvalid			( t_tvalid		    	),

    //         .r_tdata			( r_tdata  				),
    //         .r_tvalid			( r_tvalid				),
            
    //         .cs					( cs					),
    //         .sclk				( sclk   		    	),
    //         .mosi				( mosi   		    	),
    //         .miso				( miso   		    	)
    //     );
	
	//*****************************************************************************

	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	// assign t_tdata     = ( stream_enable)? t_tdata_pl :t_tdata_ps;
	// assign t_tvalid    = ( stream_enable)? t_tvalid_pl:t_tvalid_ps;
	// assign t_tready_ps = (~stream_enable)? t_tready:0;
	// assign t_tready_pl = ( stream_enable)? t_tready:0;
	
	// assign r_tdata_ps  = (~stream_enable)? r_tdata :0;
	// assign r_tvalid_ps = (~stream_enable)? r_tvalid:0;
	// assign r_tdata_pl  = ( stream_enable)? r_tdata :0;
	// assign r_tvalid_pl = ( stream_enable)? r_tvalid:0;

	// assign accel_data[15: 0] = out_x;
	// assign accel_data[31:16] = out_y;
	// assign accel_data[47:32] = out_z;


	assign bram_dout = 0;
	assign interrupt = 1'b0;
	assign accel_data = 0;
	assign accel_spi_cs = 1'b0;
	assign accel_spi_sclk = 1'b0;
	assign accel_spi_mosi = 1'b0;
	
endmodule