# do {pl_top_tb_compile.do} # ** Warning: (vlib-34) Library already exists at "modelsim_lib/work". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xilinx_vip". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xpm". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/axis_infrastructure_v1_1_0". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/axis_data_fifo_v2_0_10". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xil_defaultlib". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_utils_v3_0_10". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_pipe_v3_0_6". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_bram18k_v3_0_6". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/mult_gen_v12_0_18". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/axi_utils_v2_0_6". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6". # ** Warning: (vlib-34) Library already exists at "modelsim_lib/msim/dds_compiler_v6_0_22". # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xilinx_vip modelsim_lib/msim/xilinx_vip # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xpm modelsim_lib/msim/xpm # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap axis_infrastructure_v1_1_0 modelsim_lib/msim/axis_infrastructure_v1_1_0 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap axis_data_fifo_v2_0_10 modelsim_lib/msim/axis_data_fifo_v2_0_10 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xbip_utils_v3_0_10 modelsim_lib/msim/xbip_utils_v3_0_10 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xbip_pipe_v3_0_6 modelsim_lib/msim/xbip_pipe_v3_0_6 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xbip_bram18k_v3_0_6 modelsim_lib/msim/xbip_bram18k_v3_0_6 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap mult_gen_v12_0_18 modelsim_lib/msim/mult_gen_v12_0_18 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap axi_utils_v2_0_6 modelsim_lib/msim/axi_utils_v2_0_6 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xbip_dsp48_wrapper_v3_0_4 modelsim_lib/msim/xbip_dsp48_wrapper_v3_0_4 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xbip_dsp48_addsub_v3_0_6 modelsim_lib/msim/xbip_dsp48_addsub_v3_0_6 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap xbip_dsp48_multadd_v3_0_6 modelsim_lib/msim/xbip_dsp48_multadd_v3_0_6 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vmap 10.7 Lib Mapping Utility 2017.12 Dec 7 2017 # vmap dds_compiler_v6_0_22 modelsim_lib/msim/dds_compiler_v6_0_22 # Modifying modelsim.ini # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:52 on Jul 29,2024 # vlog -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -work xilinx_vip "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_axi4streampc.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_axi4pc.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/xil_common_vip_pkg.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_pkg.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_pkg.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi4stream_vip_if.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/axi_vip_if.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/clk_vip_if.sv C:/Xilinx/Vivado/2023.1/data/xilinx_vip/hdl/rst_vip_if.sv # -- Skipping interface axi4stream_vip_axi4streampc # -- Skipping interface axi_vip_axi4pc # -- Skipping package xil_common_vip_pkg # -- Skipping package axi4stream_vip_pkg # -- Skipping package axi_vip_pkg # -- Skipping interface axi4stream_vip_if # -- Skipping interface axi_vip_if # -- Skipping interface clk_vip_if # -- Skipping interface rst_vip_if # -- Skipping package axi4stream_vip_axi4streampc_sv_unit # # Top level modules: # --none-- # End time: 14:48:52 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:52 on Jul 29,2024 # vlog -incr -mfcu -sv -L axi_vip_v1_1_14 -L smartconnect_v1_0 -L processing_system7_vip_v1_0_16 -L xilinx_vip -work xpm "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_fifo/hdl/xpm_fifo.sv C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv # -- Skipping module xpm_cdc_single # -- Skipping module xpm_cdc_gray # -- Skipping module xpm_cdc_handshake # -- Skipping module xpm_cdc_pulse # -- Skipping module xpm_cdc_array_single # -- Skipping module xpm_cdc_sync_rst # -- Skipping module xpm_cdc_async_rst # -- Skipping module xpm_cdc_low_latency_handshake # -- Skipping module xpm_fifo_base # -- Skipping module xpm_fifo_rst # -- Skipping module xpm_counter_updn # -- Skipping module xpm_fifo_reg_vec # -- Skipping module xpm_fifo_reg_bit # -- Skipping module xpm_reg_pipe_bit # -- Skipping module xpm_fifo_sync # -- Skipping module xpm_fifo_async # -- Skipping module xpm_fifo_axis # -- Skipping module xpm_fifo_axif # -- Skipping module xpm_fifo_axil # -- Skipping module xpm_fifo_axi_reg_slice # -- Skipping module xpm_memory_base # -- Skipping module asym_bwe_bb # -- Skipping module xpm_memory_dpdistram # -- Skipping module xpm_memory_dprom # -- Skipping module xpm_memory_sdpram # -- Skipping module xpm_memory_spram # -- Skipping module xpm_memory_sprom # -- Skipping module xpm_memory_tdpram # # Top level modules: # xpm_cdc_handshake # xpm_cdc_pulse # xpm_cdc_array_single # xpm_cdc_async_rst # xpm_cdc_low_latency_handshake # xpm_fifo_sync # xpm_fifo_async # xpm_fifo_axis # xpm_fifo_axif # xpm_fifo_axil # xpm_memory_dpdistram # xpm_memory_dprom # xpm_memory_sdpram # xpm_memory_spram # xpm_memory_sprom # xpm_memory_tdpram # End time: 14:48:53 on Jul 29,2024, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:54 on Jul 29,2024 # vcom -93 -work xpm C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_VCOMP.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling package VCOMPONENTS # End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:54 on Jul 29,2024 # vlog -incr -mfcu -work axis_infrastructure_v1_1_0 "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.ip_user_files/ipstatic/hdl/axis_infrastructure_v1_1_vl_rfs.v # -- Skipping module axis_infrastructure_v1_1_0_mux_enc # -- Skipping module axis_infrastructure_v1_1_0_util_aclken_converter # -- Skipping module axis_infrastructure_v1_1_0_util_aclken_converter_wrapper # -- Skipping module axis_infrastructure_v1_1_0_util_axis2vector # -- Skipping module axis_infrastructure_v1_1_0_util_vector2axis # -- Skipping module axis_infrastructure_v1_1_0_clock_synchronizer # -- Skipping module axis_infrastructure_v1_1_0_cdc_handshake # # Top level modules: # axis_infrastructure_v1_1_0_mux_enc # axis_infrastructure_v1_1_0_util_aclken_converter_wrapper # axis_infrastructure_v1_1_0_clock_synchronizer # axis_infrastructure_v1_1_0_cdc_handshake # End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:54 on Jul 29,2024 # vlog -incr -mfcu -work axis_data_fifo_v2_0_10 "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.ip_user_files/ipstatic/hdl/axis_data_fifo_v2_0_vl_rfs.v # -- Skipping module axis_data_fifo_v2_0_10_top # # Top level modules: # axis_data_fifo_v2_0_10_top # End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:54 on Jul 29,2024 # vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w8_d128/sim/axis_data_fifo_w8_d128.v # -- Skipping module axis_data_fifo_w8_d128 # # Top level modules: # axis_data_fifo_w8_d128 # End time: 14:48:54 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:54 on Jul 29,2024 # vcom -93 -work xbip_utils_v3_0_10 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_utils_v3_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:48:55 on Jul 29,2024, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:56 on Jul 29,2024 # vcom -93 -work xbip_pipe_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_pipe_v3_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:48:56 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:56 on Jul 29,2024 # vcom -93 -work xbip_bram18k_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_bram18k_v3_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:48:58 on Jul 29,2024, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:48:58 on Jul 29,2024 # vcom -93 -work mult_gen_v12_0_18 ../../../../c64_pro.ip_user_files/ipstatic/hdl/mult_gen_v12_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:49:00 on Jul 29,2024, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:00 on Jul 29,2024 # vcom -93 -work xil_defaultlib ../../../../c64_pro.gen/sources_1/ip/mult_gen_au8_bu9_p8/sim/mult_gen_au8_bu9_p8.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity mult_gen_au8_bu9_p8 # -- Compiling architecture mult_gen_au8_bu9_p8_arch of mult_gen_au8_bu9_p8 # End time: 14:49:00 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:01 on Jul 29,2024 # vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d32/sim/axis_data_fifo_w32_d32.v # -- Skipping module axis_data_fifo_w32_d32 # # Top level modules: # axis_data_fifo_w32_d32 # End time: 14:49:01 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:01 on Jul 29,2024 # vcom -93 -work axi_utils_v2_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/axi_utils_v2_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:49:01 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:01 on Jul 29,2024 # vcom -93 -work xbip_dsp48_wrapper_v3_0_4 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:49:03 on Jul 29,2024, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:03 on Jul 29,2024 # vcom -93 -work xbip_dsp48_addsub_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:49:04 on Jul 29,2024, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:04 on Jul 29,2024 # vcom -93 -work xbip_dsp48_multadd_v3_0_6 ../../../../c64_pro.ip_user_files/ipstatic/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:49:06 on Jul 29,2024, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:06 on Jul 29,2024 # vcom -93 -work dds_compiler_v6_0_22 ../../../../c64_pro.ip_user_files/ipstatic/hdl/dds_compiler_v6_0_vh_rfs.vhd # -- Loading package STANDARD # End time: 14:49:08 on Jul 29,2024, Elapsed time: 0:00:02 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vcom 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:09 on Jul 29,2024 # vcom -93 -work xil_defaultlib ../../../../c64_pro.gen/sources_1/ip/dds_stim_16ch/sim/dds_stim_16ch.vhd # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package NUMERIC_STD # -- Compiling entity dds_stim_16ch # -- Compiling architecture dds_stim_16ch_arch of dds_stim_16ch # End time: 14:49:09 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:09 on Jul 29,2024 # vlog -incr -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" ../../../../c64_pro.gen/sources_1/ip/axis_data_fifo_w32_d16/sim/axis_data_fifo_w32_d16.v ../../../../c64_pro.srcs/sources_1/rtl/accel/accel_top.v ../../../../c64_pro.srcs/sources_1/rtl/switch/adg1414_if.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_arrange.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_if.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_mod.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/ads1299_spi.v ../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/cnv_res_collect.v ../../../../c64_pro.srcs/sources_1/rtl/utils/debouncing.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_config.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_top.v ../../../../c64_pro.srcs/sources_1/rtl/eeg/eeg_upload.v ../../../../c64_pro.srcs/sources_1/rtl/emg/emg_top.v ../../../../c64_pro.srcs/sources_1/rtl/pl_top.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_mod.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/rhs2116_top.v ../../../../c64_pro.srcs/sources_1/rtl/utils/run_time.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/sine_gen.v ../../../../c64_pro.srcs/sources_1/rtl/utils/spi_full_duplex_master.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/stim_event_collect.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/stim_monitor.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_arrange.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_distribute.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/trans_timer.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/transmit_config.v ../../../../c64_pro.srcs/sources_1/rtl/rhs2116/transmit_if.v ../../../../c64_pro.srcs/sources_1/rtl/trigger/trigger_detection.v ../../../../c64_pro.srcs/sources_1/rtl/trigger/trigger_top.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_config.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_protocol_ql.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_sort.v ../../../../c64_pro.srcs/sources_1/rtl/upload/upload_top.v ../../../../c64_pro.srcs/sources_1/rtl/pl_top_tb.v # -- Skipping module axis_data_fifo_w32_d16 # -- Skipping module accel_top # -- Skipping module adg1414_if # -- Skipping module ads1299_arrange # -- Skipping module ads1299_if # -- Skipping module ads1299_mod # -- Skipping module ads1299_spi # ** Warning: ../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch.v(27): (vlog-2600) [RDGN] - Redundant digits in numeric literal. # ** Warning: ../../../../c64_pro.srcs/sources_1/rtl/switch/channel_switch.v(28): (vlog-2600) [RDGN] - Redundant digits in numeric literal. # -- Skipping module channel_switch # -- Skipping module cnv_res_collect # -- Skipping module debouncing # -- Skipping module eeg_config # -- Skipping module eeg_top # -- Skipping module eeg_upload # -- Skipping module emg_top # -- Skipping module pl_top # -- Skipping module rhs2116_mod # -- Skipping module rhs2116_top # -- Skipping module run_time # -- Skipping module sine_gen # -- Skipping module spi_full_duplex_master # -- Skipping module stim_event_collect # -- Skipping module stim_monitor # -- Skipping module trans_arrange # -- Skipping module trans_distribute # -- Skipping module trans_timer # -- Skipping module transmit_config # -- Skipping module transmit_if # -- Skipping module trigger_detection # -- Skipping module trigger_top # -- Compiling module upload_config # -- Compiling module upload_protocol_intan # -- Skipping module upload_protocol_ql # -- Compiling module upload_sort # -- Skipping module upload_top # -- Compiling module pl_top_tb # # Top level modules: # pl_top_tb # End time: 14:49:09 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 2 # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 14:49:10 on Jul 29,2024 # vlog -work xil_defaultlib glbl.v # -- Compiling module glbl # # Top level modules: # glbl # End time: 14:49:10 on Jul 29,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0