# This file is automatically generated.
# It contains project source information necessary for synthesis and implementation.

# IP: D:/wlb_files/VivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci
# IP: The module: 'dds_stim_16ch' is the root of the design. Do not add the DONT_TOUCH constraint.

# XDC: d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'dds_stim_16ch'. Do not add the DONT_TOUCH constraint.
set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet

# IP: D:/wlb_files/VivadoPrj/c64_pro/c64_pro.srcs/sources_1/ip/dds_stim_16ch/dds_stim_16ch.xci
# IP: The module: 'dds_stim_16ch' is the root of the design. Do not add the DONT_TOUCH constraint.

# XDC: d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc
# XDC: The top module name and the constraint reference have the same name: 'dds_stim_16ch'. Do not add the DONT_TOUCH constraint.
#dup# set_property KEEP_HIERARCHY SOFT [get_cells U0 -quiet] -quiet