`timescale 1ns/1ps
 
module adg1414_if_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	localparam 		T_CLK 			= 10	;		//ns
	
	localparam		DATA_WIDTH		= 64    ;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg							clk			;
	reg							rst_n		;
	
	wire						s_tready 	;
	reg  [DATA_WIDTH - 1:0]		s_tdata		;
	reg							s_tvalid	;
	
	wire						sync		;
	wire						sclk		;
	wire						sdin		;

	reg							tx_data		;
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;

		while (1) begin
			#3_000
			@ ( posedge clk );
			s_tdata <= s_tdata + 1'b1;
			s_tvalid <= 1'b1;
			wait ( s_tready );
			@ ( posedge clk );
			s_tvalid <= 1'b0;
			@ ( posedge clk );
		end
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk			<= 1'b0	;
			rst_n		<= 1'b0	;
			
			s_tvalid	<= 1'b0	;
			s_tdata		<= {DATA_WIDTH{1'b1}}	;
			s_tdata[0]	<= 1'b0	;
		end
	endtask	
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	adg1414_if# 
		(
			.CLK_PERIOD		( 10			),
			.CLK_DIV		( 4				),
			.DATA_WIDTH		( DATA_WIDTH	)
		)
	DUT
		(
			.clk			( clk 			),
			.rst_n			( rst_n 		),

			.s_tready		( s_tready		),
			.s_tvalid		( s_tvalid   	),
			.s_tdata		( s_tdata   	),
			
			.sync			( sync   		),
			.sclk			( sclk   		),
			.sdin			( sdin   		)
		);
	
endmodule