`timescale 1 ns / 1 ps

module eeg_config#
	(
		parameter	SPIS_QTY			= 4			    	 ,
		parameter	SPI_DATA_WIDTH		= 8
	)
	(
		input							clk					 ,
		input							rst_n				 ,
		
		input		[13-1:0]			bram_addr			 ,
		input							bram_clk			 ,
		input		[32-1:0]			bram_din			 ,
		output	reg	[32-1:0]			bram_dout			 ,
		input							bram_en				 ,
		input							bram_rst			 ,
		input		[ 4-1:0]			bram_we				 ,
		
		//------------------------------------------ eeg
		output		[32-1:0]			eeg_er				 ,
		output		[32-1:0]			eeg_cr				 ,
		input		[32-1:0]			eeg_sr				 ,
		output		[32*SPIS_QTY-1:0]	eeg_tr_array		 ,
		input		[32*SPIS_QTY-1:0]	eeg_rr_array		 ,

		output	reg						eeg_sr_r_evt         

	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	BRAM_ADDR_TEST_RO				= 13'h0000;
	localparam 	BRAM_ADDR_TEST_RW				= 13'h0004;
	
	localparam 	BRAM_ADDR_EEG_ER				= 13'h0040;
	localparam 	BRAM_ADDR_EEG_CR				= 13'h0044;
	localparam 	BRAM_ADDR_EEG_SR				= 13'h0048;
	
	localparam 	BRAM_ADDR_EEG_TR				= 13'h0100;
	localparam 	BRAM_ADDR_EEG_RR				= 13'h0200;
	
	localparam 	BRAM_ADDR_EEG_TR_MASK			= 13'h1F00;
	localparam 	BRAM_ADDR_EEG_RR_MASK			= 13'h1F00;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg		[32-1:0]		test_data						;
	
	wire					bram_wr_valid					;
	wire					bram_rd_valid					;

	reg		[32-1:0]		eeg_er_r						;
	reg		[32-1:0]		eeg_cr_r						;
	reg		[32-1:0]		eeg_tr_r[SPIS_QTY-1:0]			;
	wire	[32-1:0]		eeg_rr_r[SPIS_QTY-1:0]			;
	
	integer	n;
	
	genvar i;
	
	//*****************************************************************************
	// Procedural blocks
	//*****************************************************************************

	//write bram/Set config
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			test_data <= 0;
		else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_TEST_RW ) )
			test_data <= bram_din;
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			eeg_er_r <= 0;
		end else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_EEG_ER ) ) begin
			eeg_er_r <= bram_din;
		end else begin
			eeg_er_r <= 0;
		end
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			eeg_cr_r <= 0;
		end else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_EEG_CR ) ) begin
			eeg_cr_r <= bram_din;
		end
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			n = 0;
			while(n<SPIS_QTY) begin
				eeg_tr_r[n] <= 0;
				n = n + 1;
			end
		end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_EEG_TR_MASK) == BRAM_ADDR_EEG_TR ) )
			eeg_tr_r[bram_addr[7:2]] <= bram_din;
	end
	
	//read bram/Get config
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			bram_dout <= 0;
		end else if ( bram_rd_valid ) begin
			
			if ( bram_addr  == BRAM_ADDR_TEST_RO )
				bram_dout <= 32'h12345678;
			
			if ( bram_addr  == BRAM_ADDR_TEST_RW )
				bram_dout <= test_data;
			
			if ( bram_addr  == BRAM_ADDR_EEG_SR ) begin
				bram_dout <= eeg_sr;
				eeg_sr_r_evt <= 1'b1;
			end
			
			if ( (bram_addr & BRAM_ADDR_EEG_RR_MASK) == BRAM_ADDR_EEG_RR )
				bram_dout <= eeg_rr_r[bram_addr[7:2]];
			
		end
	end

	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			eeg_sr_r_evt <= 1'b0;
		else if ( bram_wr_valid && ( bram_addr  == BRAM_ADDR_EEG_SR ) )
			eeg_sr_r_evt <= 1'b1;
		else
			eeg_sr_r_evt <= 1'b0;
	end
	
	//*****************************************************************************
	// Continuous assignments
	//*****************************************************************************
	assign bram_wr_valid = bram_en && (bram_we == 4'hF);
	assign bram_rd_valid = bram_en && (bram_we == 4'h0);
	
	generate
		for(i=0;i<SPIS_QTY;i=i+1) begin : mapping
			assign eeg_tr_array[32*i+31 : 32*i] = eeg_tr_r[i];
			assign eeg_rr_r[i] = eeg_rr_array[32*i+31 : 32*i];
		end
	endgenerate

	assign eeg_er = eeg_er_r;
	assign eeg_cr = eeg_cr_r;
	
endmodule