# // ModelSim SE-64 10.7 Dec 7 2017 # // # // Copyright 1991-2017 Mentor Graphics Corporation # // All Rights Reserved. # // # // ModelSim SE-64 and its associated documentation contain trade # // secrets and commercial or financial information that are the property of # // Mentor Graphics Corporation and are privileged, confidential, # // and exempt from disclosure under the Freedom of Information Act, # // 5 U.S.C. Section 552. Furthermore, this information # // is prohibited from disclosure under the Trade Secrets Act, # // 18 U.S.C. Section 1905. # // # do {pl_top_tb_simulate.do} # vsim -voptargs=""+acc"" -L xil_defaultlib -L xilinx_vip -L xpm -L axis_infrastructure_v1_1_0 -L axis_data_fifo_v2_0_10 -L xbip_utils_v3_0_10 -L xbip_pipe_v3_0_6 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_18 -L axi_utils_v2_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_6 -L xbip_dsp48_multadd_v3_0_6 -L dds_compiler_v6_0_22 -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.pl_top_tb xil_defaultlib.glbl # Start time: 14:49:21 on Jul 29,2024 # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Note: (vopt-143) Recognized 1 FSM in module "upload_sort(fast)". # ** Note: (vopt-143) Recognized 1 FSM in module "upload_protocol_intan(fast)". # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. # 1 # 1 # ** Warning: (vsim-WLF-5000) WLF file currently in use: vsim.wlf # File in use by: wenlibin Hostname: 840-5CG14025H4 ProcessID: 17156 # Attempting to use alternate WLF file "./wlftw63818". # ** Warning: (vsim-WLF-5001) Could not open WLF file: vsim.wlf # Using alternate file: ./wlftw63818 # .main_pane.wave.interior.cs.body.pw.wf # .main_pane.structure.interior.cs.body.struct # .main_pane.objects.interior.cs.body.tree # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run restart -f # ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. add wave -position insertpoint \ sim:/pl_top_tb/DUT/u_rhs2116_top/VERSION \ sim:/pl_top_tb/DUT/u_rhs2116_top/CLK_PERIOD \ sim:/pl_top_tb/DUT/u_rhs2116_top/SPI_CLK_DIV \ sim:/pl_top_tb/DUT/u_rhs2116_top/SPI_DATA_WIDTH \ sim:/pl_top_tb/DUT/u_rhs2116_top/SPI_TRANS_PERIOD \ sim:/pl_top_tb/DUT/u_rhs2116_top/CHIPSET_QTY \ sim:/pl_top_tb/DUT/u_rhs2116_top/CH_OF_CHIPSET \ sim:/pl_top_tb/DUT/u_rhs2116_top/REG_ADDR_STIM_POL \ sim:/pl_top_tb/DUT/u_rhs2116_top/REG_ADDR_POS_CUR \ sim:/pl_top_tb/DUT/u_rhs2116_top/REG_ADDR_NEG_CUR \ sim:/pl_top_tb/DUT/u_rhs2116_top/clk \ sim:/pl_top_tb/DUT/u_rhs2116_top/rst_n \ sim:/pl_top_tb/DUT/u_rhs2116_top/bram_addr \ sim:/pl_top_tb/DUT/u_rhs2116_top/bram_clk \ sim:/pl_top_tb/DUT/u_rhs2116_top/bram_din \ sim:/pl_top_tb/DUT/u_rhs2116_top/bram_dout \ sim:/pl_top_tb/DUT/u_rhs2116_top/bram_en \ sim:/pl_top_tb/DUT/u_rhs2116_top/bram_rst \ sim:/pl_top_tb/DUT/u_rhs2116_top/bram_we \ sim:/pl_top_tb/DUT/u_rhs2116_top/interrupt \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_event_code \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_txd_tdata \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_txd_tlast \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_txd_tready \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_txd_tvalid \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_rxd_tdata \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_rxd_tlast \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_rxd_tready \ sim:/pl_top_tb/DUT/u_rhs2116_top/axi_str_rxd_tvalid \ sim:/pl_top_tb/DUT/u_rhs2116_top/sw_enable \ sim:/pl_top_tb/DUT/u_rhs2116_top/sw_data_sel \ sim:/pl_top_tb/DUT/u_rhs2116_top/sw_data_0 \ sim:/pl_top_tb/DUT/u_rhs2116_top/sw_data_1 \ sim:/pl_top_tb/DUT/u_rhs2116_top/sw_state \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_en \ sim:/pl_top_tb/DUT/u_rhs2116_top/cs \ sim:/pl_top_tb/DUT/u_rhs2116_top/sclk \ sim:/pl_top_tb/DUT/u_rhs2116_top/mosi \ sim:/pl_top_tb/DUT/u_rhs2116_top/miso \ sim:/pl_top_tb/DUT/u_rhs2116_top/debug_sig \ sim:/pl_top_tb/DUT/u_rhs2116_top/update_period \ sim:/pl_top_tb/DUT/u_rhs2116_top/enable_timer \ sim:/pl_top_tb/DUT/u_rhs2116_top/dds_by_ps \ sim:/pl_top_tb/DUT/u_rhs2116_top/dds_aclken_ps \ sim:/pl_top_tb/DUT/u_rhs2116_top/dds_aresetn_ps \ sim:/pl_top_tb/DUT/u_rhs2116_top/dds_aclken_pl \ sim:/pl_top_tb/DUT/u_rhs2116_top/dds_aresetn_pl \ sim:/pl_top_tb/DUT/u_rhs2116_top/dds_aclken \ sim:/pl_top_tb/DUT/u_rhs2116_top/dds_aresetn \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_trim_p_array_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_trim_n_array_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_trim_p_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_trim_n_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/phase_enable \ sim:/pl_top_tb/DUT/u_rhs2116_top/phase_inc_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/phase_off_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/sine_wave_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_cmd_valid_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_cmd_data_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_cmd_ready_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_res_en_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_res_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_cmd_valid \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_cmd_data \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_cmd_ready \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_res_en \ sim:/pl_top_tb/DUT/u_rhs2116_top/spi_res \ sim:/pl_top_tb/DUT/u_rhs2116_top/trans_round \ sim:/pl_top_tb/DUT/u_rhs2116_top/trans_pulse \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tdata_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tlast_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tready_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tvalid_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tdata \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tlast \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tready \ sim:/pl_top_tb/DUT/u_rhs2116_top/axis_ctrl_tvalid \ sim:/pl_top_tb/DUT/u_rhs2116_top/record_ch_qty \ sim:/pl_top_tb/DUT/u_rhs2116_top/m_axi_trans_tdata \ sim:/pl_top_tb/DUT/u_rhs2116_top/m_axi_trans_tlast \ sim:/pl_top_tb/DUT/u_rhs2116_top/m_axi_trans_tready \ sim:/pl_top_tb/DUT/u_rhs2116_top/m_axi_trans_tvalid \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tdata \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tlast \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tready \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tvalid \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tdata_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tlast_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tready_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/cnv_res_tvalid_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/monitor_data \ sim:/pl_top_tb/DUT/u_rhs2116_top/monitor_data_array \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_monitor_rt \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_monitor_latch \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_state \ sim:/pl_top_tb/DUT/u_rhs2116_top/stim_stage_code \ sim:/pl_top_tb/DUT/u_rhs2116_top/event_in_arrary run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 10:15:14 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # -- Compiling module pl_top_tb # # Top level modules: # pl_top_tb # End time: 10:15:14 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 restart -f # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 add wave -position insertpoint \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/CLK_PERIOD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/CHANNLE_QTY \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ST_IDLE \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ST_RX \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ST_SCAN \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ST_TX \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/clk \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/rst_n \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/eeg_sel \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/protocol_sel \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ch_mapping2pc_array \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/upload_ch_array \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg16_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg16_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg16_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg16_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg24_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg24_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg24_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eeg24_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eeg_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eeg_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eeg_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eeg_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/debug_sig_sort \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eegX_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eegX_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eegX_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/s_axis_eegX_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ch_map2pc \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ch_map2intan \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ch_pl \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ch_pc \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/cstate \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/nstate \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/record_rx \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/record_tx \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/byte_tx \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ch_list \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/ch \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/bytes \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/byte_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eegY_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eegY_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eegY_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/m_axis_eegY_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_sort/j restart -f # ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 add wave -position insertpoint \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_eeg_tlast \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_eeg_tready \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_eeg_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_eeg_ql_tready \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_eeg_intan_tready restart -f # ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 11:29:49 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_protocol_intan.v # -- Compiling module upload_protocol_intan # # Top level modules: # upload_protocol_intan # End time: 11:29:49 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 add wave -position insertpoint \ sim:/pl_top_tb/T_CLK \ sim:/pl_top_tb/RSH2116_QTY \ sim:/pl_top_tb/EEG_ADS1299_QTY \ sim:/pl_top_tb/EEG_ADS1299_SPI_QTY \ sim:/pl_top_tb/EEG_BRAM_ADDR_TEST_RO \ sim:/pl_top_tb/EEG_BRAM_ADDR_TEST_RW \ sim:/pl_top_tb/EEG_BRAM_ADDR_EEG_ER \ sim:/pl_top_tb/EEG_BRAM_ADDR_EEG_CR \ sim:/pl_top_tb/EEG_BRAM_ADDR_EEG_SR \ sim:/pl_top_tb/EEG_BRAM_ADDR_EEG_TR \ sim:/pl_top_tb/EEG_BRAM_ADDR_EEG_RR \ sim:/pl_top_tb/EEG_BRAM_ADDR_EEG_TR_MASK \ sim:/pl_top_tb/EEG_BRAM_ADDR_EEG_RR_MASK \ sim:/pl_top_tb/CMD_CNV \ sim:/pl_top_tb/CMD_STIM \ sim:/pl_top_tb/CMD_NULL \ sim:/pl_top_tb/CMD_END \ sim:/pl_top_tb/CMD_WRITE \ sim:/pl_top_tb/CMD_READ \ sim:/pl_top_tb/STIM_POL_REG_ADDR \ sim:/pl_top_tb/POS_CUR_REG_ADDR \ sim:/pl_top_tb/NEG_CUR_REG_ADDR \ sim:/pl_top_tb/BRAM_ADDR_TEST_RW \ sim:/pl_top_tb/BRAM_ADDR_TEST_RO_DATA \ sim:/pl_top_tb/BRAM_ADDR_TEST_VERSION \ sim:/pl_top_tb/BRAM_ADDR_UPDATE_PERIOD \ sim:/pl_top_tb/BRAM_ADDR_UPLOAD_ROUND_NUM \ sim:/pl_top_tb/BRAM_ADDR_ENABLE \ sim:/pl_top_tb/BRAM_ADDR_RESET \ sim:/pl_top_tb/BRAM_ADDR_DDS_PHASE_TRIG \ sim:/pl_top_tb/BRAM_ADDR_SWITCH_CTRL \ sim:/pl_top_tb/BRAM_ADDR_SWITCH_DATA0 \ sim:/pl_top_tb/BRAM_ADDR_SWITCH_DATA1 \ sim:/pl_top_tb/BRAM_ADDR_UPLOAD_TIMEOUT \ sim:/pl_top_tb/BRAM_ADDR_SPI_STATE_START \ sim:/pl_top_tb/BRAM_ADDR_SPI_TX_START \ sim:/pl_top_tb/BRAM_ADDR_SPI_RX_START \ sim:/pl_top_tb/BRAM_ADDR_SPI_ERR_START \ sim:/pl_top_tb/BRAM_ADDR_DDS_PHASE_INC_START \ sim:/pl_top_tb/BRAM_ADDR_DDS_PHASE_OFF_START \ sim:/pl_top_tb/BRAM_ADDR_CHIP_0_CNV_CMD_LTH \ sim:/pl_top_tb/BRAM_ADDR_CHIP_1_CNV_CMD_LTH \ sim:/pl_top_tb/BRAM_ADDR_CHIP_2_CNV_CMD_LTH \ sim:/pl_top_tb/BRAM_ADDR_CHIP_3_CNV_CMD_LTH \ sim:/pl_top_tb/BRAM_ADDR_STIM_TRIM_P_MASK \ sim:/pl_top_tb/BRAM_ADDR_STIM_TRIM_P_START \ sim:/pl_top_tb/BRAM_ADDR_STIM_TRIM_N_MASK \ sim:/pl_top_tb/BRAM_ADDR_STIM_TRIM_N_START \ sim:/pl_top_tb/BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_P \ sim:/pl_top_tb/BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_P \ sim:/pl_top_tb/BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_P \ sim:/pl_top_tb/BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_P \ sim:/pl_top_tb/BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_N \ sim:/pl_top_tb/BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_N \ sim:/pl_top_tb/BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_N \ sim:/pl_top_tb/BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_N \ sim:/pl_top_tb/BRAM_ADDR_CHIP_0_CNV_CMD_START \ sim:/pl_top_tb/BRAM_ADDR_CHIP_1_CNV_CMD_START \ sim:/pl_top_tb/BRAM_ADDR_CHIP_2_CNV_CMD_START \ sim:/pl_top_tb/BRAM_ADDR_CHIP_3_CNV_CMD_START \ sim:/pl_top_tb/COVER_Y \ sim:/pl_top_tb/COVER_N \ sim:/pl_top_tb/STAGE_SS \ sim:/pl_top_tb/STAGE_RE \ sim:/pl_top_tb/STAGE_FS \ sim:/pl_top_tb/STAGE_EE \ sim:/pl_top_tb/CHIP_0 \ sim:/pl_top_tb/CHIP_1 \ sim:/pl_top_tb/CHIP_2 \ sim:/pl_top_tb/CHIP_3 \ sim:/pl_top_tb/CHANNEL_0 \ sim:/pl_top_tb/CHANNEL_1 \ sim:/pl_top_tb/CHANNEL_2 \ sim:/pl_top_tb/CHANNEL_3 \ sim:/pl_top_tb/CHANNEL_4 \ sim:/pl_top_tb/CHANNEL_5 \ sim:/pl_top_tb/CHANNEL_6 \ sim:/pl_top_tb/CHANNEL_7 \ sim:/pl_top_tb/CHANNEL_8 \ sim:/pl_top_tb/CHANNEL_9 \ sim:/pl_top_tb/CHANNEL_A \ sim:/pl_top_tb/CHANNEL_B \ sim:/pl_top_tb/CHANNEL_C \ sim:/pl_top_tb/CHANNEL_D \ sim:/pl_top_tb/CHANNEL_E \ sim:/pl_top_tb/CHANNEL_F \ sim:/pl_top_tb/DDS_CH_0 \ sim:/pl_top_tb/DDS_CH_1 \ sim:/pl_top_tb/DDS_CH_2 \ sim:/pl_top_tb/DDS_CH_3 \ sim:/pl_top_tb/DDS_CH_4 \ sim:/pl_top_tb/DDS_CH_5 \ sim:/pl_top_tb/DDS_CH_6 \ sim:/pl_top_tb/DDS_CH_7 \ sim:/pl_top_tb/DDS_CH_8 \ sim:/pl_top_tb/DDS_CH_9 \ sim:/pl_top_tb/DDS_CH_A \ sim:/pl_top_tb/DDS_CH_B \ sim:/pl_top_tb/DDS_CH_C \ sim:/pl_top_tb/DDS_CH_D \ sim:/pl_top_tb/DDS_CH_E \ sim:/pl_top_tb/DDS_CH_F \ sim:/pl_top_tb/GAIN_MAX \ sim:/pl_top_tb/BRAM_ADDR_MSG_TEST_RO \ sim:/pl_top_tb/BRAM_ADDR_MSG_TEST_RW \ sim:/pl_top_tb/BRAM_ADDR_MSG_SEL_EEG24 \ sim:/pl_top_tb/BRAM_ADDR_MSG_ROUNDS_QTY \ sim:/pl_top_tb/BRAM_ADDR_MSG_PRE_MSG_LTH \ sim:/pl_top_tb/BRAM_ADDR_MSG_PRE_MSG_START \ sim:/pl_top_tb/BRAM_ADDR_MSG_CH_MAP_START \ sim:/pl_top_tb/BRAM_ADDR_MSG_UPLOAD_CH_START \ sim:/pl_top_tb/clk \ sim:/pl_top_tb/rst_n \ sim:/pl_top_tb/bram_stim_addr \ sim:/pl_top_tb/bram_stim_clk \ sim:/pl_top_tb/bram_stim_din \ sim:/pl_top_tb/bram_stim_dout \ sim:/pl_top_tb/bram_stim_en \ sim:/pl_top_tb/bram_stim_rst \ sim:/pl_top_tb/bram_stim_we \ sim:/pl_top_tb/bram_eeg_addr \ sim:/pl_top_tb/bram_eeg_clk \ sim:/pl_top_tb/bram_eeg_din \ sim:/pl_top_tb/bram_eeg_dout \ sim:/pl_top_tb/bram_eeg_en \ sim:/pl_top_tb/bram_eeg_rst \ sim:/pl_top_tb/bram_eeg_we \ sim:/pl_top_tb/bram_emg_addr \ sim:/pl_top_tb/bram_emg_clk \ sim:/pl_top_tb/bram_emg_din \ sim:/pl_top_tb/bram_emg_dout \ sim:/pl_top_tb/bram_emg_en \ sim:/pl_top_tb/bram_emg_rst \ sim:/pl_top_tb/bram_emg_we \ sim:/pl_top_tb/bram_accel_addr \ sim:/pl_top_tb/bram_accel_clk \ sim:/pl_top_tb/bram_accel_din \ sim:/pl_top_tb/bram_accel_dout \ sim:/pl_top_tb/bram_accel_en \ sim:/pl_top_tb/bram_accel_rst \ sim:/pl_top_tb/bram_accel_we \ sim:/pl_top_tb/bram_msg_addr \ sim:/pl_top_tb/bram_msg_clk \ sim:/pl_top_tb/bram_msg_din \ sim:/pl_top_tb/bram_msg_dout \ sim:/pl_top_tb/bram_msg_en \ sim:/pl_top_tb/bram_msg_rst \ sim:/pl_top_tb/bram_msg_we \ sim:/pl_top_tb/stim_int \ sim:/pl_top_tb/eeg_int \ sim:/pl_top_tb/emg_int \ sim:/pl_top_tb/accel_int \ sim:/pl_top_tb/m_axis_stim_tdata \ sim:/pl_top_tb/m_axis_stim_tlast \ sim:/pl_top_tb/m_axis_stim_tready \ sim:/pl_top_tb/m_axis_stim_tvalid \ sim:/pl_top_tb/m_axis_record_tfull \ sim:/pl_top_tb/m_axis_record_tdata \ sim:/pl_top_tb/m_axis_record_tkeep \ sim:/pl_top_tb/m_axis_record_tlast \ sim:/pl_top_tb/m_axis_record_tready \ sim:/pl_top_tb/m_axis_record_tvalid \ sim:/pl_top_tb/rsh2116_enable \ sim:/pl_top_tb/rsh2116_spi_cs \ sim:/pl_top_tb/rsh2116_spi_sclk \ sim:/pl_top_tb/rsh2116_spi_mosi \ sim:/pl_top_tb/rsh2116_spi_miso \ sim:/pl_top_tb/eeg_ads1299_spi_cs \ sim:/pl_top_tb/eeg_ads1299_spi_sclk \ sim:/pl_top_tb/eeg_ads1299_spi_mosi \ sim:/pl_top_tb/eeg_ads1299_spi_miso \ sim:/pl_top_tb/eeg_ads1299_drdy_n \ sim:/pl_top_tb/eeg_ads1299_start \ sim:/pl_top_tb/emg_ads1299_spi_cs \ sim:/pl_top_tb/emg_ads1299_spi_sclk \ sim:/pl_top_tb/emg_ads1299_spi_mosi \ sim:/pl_top_tb/emg_ads1299_spi_miso \ sim:/pl_top_tb/emg_ads1299_drdy_n \ sim:/pl_top_tb/emg_ads1299_start \ sim:/pl_top_tb/emg_ads1299_reset_n \ sim:/pl_top_tb/emg_ads1299_pwdn_n \ sim:/pl_top_tb/accel_spi_cs \ sim:/pl_top_tb/accel_spi_sclk \ sim:/pl_top_tb/accel_spi_mosi \ sim:/pl_top_tb/accel_spi_miso \ sim:/pl_top_tb/accel_int0 \ sim:/pl_top_tb/accel_int1 \ sim:/pl_top_tb/adg1414_spi_sync \ sim:/pl_top_tb/adg1414_spi_sclk \ sim:/pl_top_tb/adg1414_spi_mosi \ sim:/pl_top_tb/trigger_reset \ sim:/pl_top_tb/trigger_in \ sim:/pl_top_tb/trigger_out \ sim:/pl_top_tb/s_axis_tdata \ sim:/pl_top_tb/s_axis_tlast \ sim:/pl_top_tb/s_axis_tready \ sim:/pl_top_tb/s_axis_tvalid \ sim:/pl_top_tb/emg_ads1299_cs_w \ sim:/pl_top_tb/emg_ads1299_sclk_w \ sim:/pl_top_tb/emg_ads1299_mosi_w \ sim:/pl_top_tb/emg_ads1299_miso_w \ sim:/pl_top_tb/emg_ads1299_drdy_w \ sim:/pl_top_tb/emg_ads1299_start_w \ sim:/pl_top_tb/no_enable \ sim:/pl_top_tb/temp32 \ sim:/pl_top_tb/msg_byte_cnt \ sim:/pl_top_tb/msg_head_valid \ sim:/pl_top_tb/n restart -f # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Note: (vopt-143) Recognized 1 FSM in module "upload_protocol_intan(fast)". # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 add wave -position insertpoint \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/CLK_PERIOD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/CHANNLE_QTY \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/PRE_MSG_LEN \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_IDLE \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_MSG_HEAD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_WAIT \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_READ_TRIGGER \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_MSG_TRIGGER \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_MSG_RECORD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_MSG_CRC \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ST_ADDITIONAL \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/ADDL_NUM \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/clk \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/rst_n \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/enable \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/interrupt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/pulse_ms \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/run_time_ms \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/pre_message_array \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/pre_message_length \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_round_qty_set \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/reset_package_id \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/package_overtime_ms \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/s_axis_trigger_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/s_axis_trigger_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/s_axis_trigger_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/s_axis_eeg_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/s_axis_eeg_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/s_axis_eeg_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/s_axis_eeg_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/accel_data \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/m_axis_record_tfull \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/m_axis_record_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/m_axis_record_tkeep \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/m_axis_record_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/m_axis_record_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/m_axis_record_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/cstate \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/nstate \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/overtime_ms \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/package_id \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/pre_message \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/trigger_word \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/trigger_byte \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/msg_crc \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_round_qty \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_bytes_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_bytes_cnt_add1 \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_rounds_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_record_bytes_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/crc16_out \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/crc16 \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_addl \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/byte_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_break \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/upload_disable \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_ql/debug_sig_sort restart -f # ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run add wave -position insertpoint \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_record_tfull \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_record_tdata \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_record_tkeep \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_record_tlast \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_record_tready \ sim:/pl_top_tb/DUT/u_upload_top/m_axis_record_tvalid restart -f # ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run # Causality operation skipped due to absence of debug database file vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 19:06:19 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # -- Compiling module pl_top_tb # # Top level modules: # pl_top_tb # End time: 19:06:19 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 restart -f # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. restart -f # ** Note: (vsim-8009) Loading existing optimized design _opt1 # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 19:08:14 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v # -- Compiling module upload_top # # Top level modules: # upload_top # End time: 19:08:14 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 restart -f # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v(195): (vopt-2685) [TFMPC] - Too few port connections for 'u_upload_protocol_ql'. Expected 25, found 24. # ** Warning: D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_top.v(195): (vopt-2718) [TFMPC] - Missing connection for port 'interrupt'. # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. add wave -position insertpoint \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/CLK_PERIOD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/CHANNLE_QTY \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_IDLE \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_WAIT \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_HEAD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_DATA_H \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_RECORD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_DATA_T \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_REG_VAL \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_DA_AD \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_TRIG_IN \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_TRIG_OUT \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_MSG_CRC \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ST_ADDITIONAL \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/HEAD_LTH \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/REG_LTH \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/DA_AD_LTH \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/TRIG_IN_LTH \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/TRIG_OUT_LTH \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/ADDL_LTH \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/clk \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/rst_n \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/enable \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/interrupt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/pulse_ms \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_round_qty_set \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/reset_package_id \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/package_overtime_ms \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/s_axis_trigger_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/s_axis_trigger_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/s_axis_trigger_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/s_axis_eeg_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/s_axis_eeg_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/s_axis_eeg_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/s_axis_eeg_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/m_axis_record_tfull \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/m_axis_record_tdata \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/m_axis_record_tkeep \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/m_axis_record_tlast \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/m_axis_record_tready \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/m_axis_record_tvalid \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/cstate \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/nstate \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/msg_head \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/package_id \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/overtime_ms \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/trigger_word \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/trigger_in_byte \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/msg_crc \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_round_qty \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_rounds_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_bytes_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_bytes_cnt_add1 \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_record_bytes_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/crc16_out \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/crc16 \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_addl \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/byte_cnt \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_break \ sim:/pl_top_tb/DUT/u_upload_top/u_upload_protocol_intan/upload_disable run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 19:21:29 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # -- Compiling module pl_top_tb # # Top level modules: # pl_top_tb # End time: 19:21:29 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 restart -f # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 19:36:24 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/pl_top_tb.v # -- Compiling module pl_top_tb # # Top level modules: # pl_top_tb # End time: 19:36:24 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 19:36:25 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v # -- Compiling module upload_sort # # Top level modules: # upload_sort # End time: 19:36:25 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 restart -f # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Note: (vopt-143) Recognized 1 FSM in module "upload_sort(fast)". # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 19:45:16 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v # -- Compiling module upload_sort # # Top level modules: # upload_sort # End time: 19:45:16 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 vlog -mfcu -work xil_defaultlib +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog +incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl +incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl +incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v # Model Technology ModelSim SE-64 vlog 10.7 Compiler 2017.12 Dec 7 2017 # Start time: 19:45:28 on Jul 30,2024 # vlog -reportprogress 300 -mfcu -work xil_defaultlib "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/ec67/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/aed8/hdl" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/f0b6/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/66be/hdl/verilog" "+incdir+../../../../c64_pro.gen/sources_1/bd/design_a9_1/ipshared/8713/hdl" "+incdir+../../../../c64_pro.ip_user_files/ipstatic/hdl" "+incdir+C:/Xilinx/Vivado/2023.1/data/xilinx_vip/include" -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact D:/projects/vivadoPrj/c64_pro/c64_pro.srcs/sources_1/rtl/upload/upload_sort.v # -- Compiling module upload_sort # # Top level modules: # upload_sort # End time: 19:45:28 on Jul 30,2024, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 restart -f # ** Note: (vsim-3813) Design is being optimized due to module recompilation... # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_axis', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_fifo_reg_bit', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_counter_updn', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_memory_base', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L axi_vip_v1_1_14' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L smartconnect_v1_0' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Warning: (vopt-10016) Option '-L processing_system7_vip_v1_0_16' was detected by vlog for design-unit 'xpm_cdc_sync_rst', but was not detected by vopt. The vlog option will be ignored. # ** Note: (vopt-143) Recognized 1 FSM in module "upload_sort(fast)". # Loading work.pl_top_tb(fast) # Loading work.axis_data_fifo_w32_d32(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast) # Loading sv_std.std # Loading xpm.xpm_fifo_axis(fast) # Loading xpm.xpm_cdc_sync_rst(fast) # Loading xpm.xpm_fifo_base(fast) # Loading xpm.xpm_fifo_rst(fast) # Loading xpm.xpm_fifo_reg_bit(fast) # Loading xpm.xpm_counter_updn(fast) # Loading xpm.xpm_counter_updn(fast__1) # Loading xpm.xpm_counter_updn(fast__2) # Loading xpm.xpm_memory_base(fast) # Loading xpm.xpm_counter_updn(fast__3) # Loading work.pl_top(fast) # Loading work.trigger_top(fast) # Loading work.debouncing(fast) # Loading work.trigger_detection(fast) # Loading work.axis_data_fifo_w32_d16(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__1) # Loading xpm.xpm_fifo_axis(fast__1) # Loading xpm.xpm_fifo_base(fast__1) # Loading xpm.xpm_counter_updn(fast__4) # Loading xpm.xpm_counter_updn(fast__5) # Loading xpm.xpm_counter_updn(fast__6) # Loading xpm.xpm_memory_base(fast__1) # Loading work.rhs2116_top(fast) # Loading work.transmit_config(fast) # Loading work.trans_timer(fast) # Loading work.sine_gen(fast) # Loading work.trans_distribute(fast) # Loading work.trans_arrange(fast) # Loading work.transmit_if(fast) # Loading work.spi_full_duplex_master(fast) # Loading work.cnv_res_collect(fast) # Loading work.stim_event_collect(fast) # Loading work.stim_monitor(fast) # Loading work.eeg_top(fast) # Loading work.eeg_config(fast) # Loading work.ads1299_arrange(fast) # Loading work.ads1299_if(fast) # Loading work.ads1299_spi(fast) # Loading work.eeg_upload(fast) # Loading work.emg_top(fast) # Loading work.accel_top(fast) # Loading work.channel_switch(fast) # Loading work.adg1414_if(fast) # Loading work.upload_top(fast) # Loading work.run_time(fast) # Loading work.upload_config(fast) # Loading work.upload_sort(fast) # Loading work.axis_data_fifo_w8_d128(fast) # Loading axis_data_fifo_v2_0_10.axis_data_fifo_v2_0_10_top(fast__2) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_aclken_converter_wrapper(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_axis2vector(fast__1) # Loading axis_infrastructure_v1_1_0.axis_infrastructure_v1_1_0_util_vector2axis(fast__1) # Loading xpm.xpm_fifo_axis(fast__2) # Loading xpm.xpm_fifo_base(fast__2) # Loading xpm.xpm_counter_updn(fast__7) # Loading xpm.xpm_counter_updn(fast__8) # Loading xpm.xpm_counter_updn(fast__9) # Loading xpm.xpm_memory_base(fast__2) # Loading work.upload_protocol_ql(fast) # Loading work.upload_protocol_intan(fast) # Loading work.rhs2116_mod(fast) # Loading work.ads1299_mod(fast) # Loading work.glbl(fast) # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading ieee.numeric_std(body) # Loading work.dds_stim_16ch(dds_stim_16ch_arch)#1 # Loading ieee.std_logic_arith(body) # Loading ieee.std_logic_signed(body) # Loading ieee.math_real(body) # Loading ieee.std_logic_unsigned(body) # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading unisim.vpkg(body) # Loading unisim.fdse(fdse_v)#1 # Loading unisim.fdre(fdre_v)#1 # Loading work.mult_gen_au8_bu9_p8(mult_gen_au8_bu9_p8_arch)#1 # Loading unisim.mult_and(mult_and_v)#1 # Loading unisim.lut2(lut2_v)#1 # Loading unisim.muxcy(muxcy_v)#1 # Loading unisim.xorcy(xorcy_v)#1 # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[3]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[2]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[1]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/////(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0//(1 downto 0), and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/transmit_arrange[0]/u_trans_arrange/u_mult_gain/U0/(1 downto 0). # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//////, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///. # ** Warning: (vsim-8684) No drivers exist on out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///, and its initial value is not used. # Therefore, simulation behavior may occur that is not in compliance with # the VHDL standard as the initial values come from the base signal /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0//. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(8) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(7) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(6) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(5) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(4) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(3) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(2) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(1) has no driver. # This port will contribute value (U) to the signal network. # ** Warning: (vsim-8683) Uninitialized out port /pl_top_tb/DUT/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0///(0) has no driver. # This port will contribute value (U) to the signal network. run # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.u_axis_stream_data_fifo_rs.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_trigger_top.u_trigger_fifo.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[0].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[1].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[2].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_rhs2116_top.u_trans_distribute.output_fifo[3].u_axis_data_fifo_if_recv.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 # ** Info: [XPM_MEMORY 20-1] MEMORY_PRIMITIVE (0) instructs Vivado Synthesis to choose the memory primitive type. Depending on their values, other XPM_MEMORY parameters may preclude the choice of certain memory primitive types. Review XPM_MEMORY documentation and parameter values to understand any limitations, or set MEMORY_PRIMITIVE to a different value. pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc # Time: 1 ps Scope: pl_top_tb.DUT.u_upload_top.u_upload_sort.u_axis_data_fifo_w8_d128.inst.gen_fifo.xpm_fifo_axis_inst.xpm_fifo_base_inst.gen_sdpram.xpm_memory_base_inst.config_drc File: C:/Xilinx/Vivado/2023.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv Line: 508 run # End time: 18:39:15 on Jul 31,2024, Elapsed time: 51:49:54 # Errors: 0, Warnings: 1