Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
| Date             : Fri Sep  4 15:41:33 2026
| Host             : DESKTOP-VN054CM running 64-bit major release  (build 9200)
| Command          : report_power -file c64pro_top_power_routed.rpt -pb c64pro_top_power_summary_routed.pb -rpx c64pro_top_power_routed.rpx
| Design           : c64pro_top
| Device           : xc7z020clg400-2
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 1.582        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 1.431        |
| Device Static (W)        | 0.151        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 66.7         |
| Junction Temperature (C) | 43.3         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |     0.099 |        4 |       --- |             --- |
| Slice Logic              |     0.038 |    70198 |       --- |             --- |
|   LUT as Logic           |     0.034 |    21761 |     53200 |           40.90 |
|   Register               |     0.002 |    33794 |    106400 |           31.76 |
|   CARRY4                 |     0.001 |      988 |     13300 |            7.43 |
|   F7/F8 Muxes            |    <0.001 |     2664 |     53200 |            5.01 |
|   LUT as Distributed RAM |    <0.001 |      558 |     17400 |            3.21 |
|   LUT as Shift Register  |    <0.001 |     1005 |     17400 |            5.78 |
|   Others                 |     0.000 |     3660 |       --- |             --- |
| Signals                  |     0.050 |    46880 |       --- |             --- |
| Block RAM                |     0.062 |      105 |       140 |           75.00 |
| I/O                      |     0.008 |       58 |       125 |           46.40 |
| PS7                      |     1.175 |        1 |       --- |             --- |
| Static Power             |     0.151 |          |           |                 |
| Total                    |     1.582 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.261 |       0.244 |      0.018 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.015 |       0.000 |      0.015 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.012 |       0.005 |      0.007 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccpint   |       1.000 |     0.707 |       0.678 |      0.029 |       NA    | Unspecified | NA         |
| Vccpaux   |       1.800 |     0.035 |       0.025 |      0.010 |       NA    | Unspecified | NA         |
| Vccpll    |       1.800 |     0.017 |       0.014 |      0.003 |       NA    | Unspecified | NA         |
| Vcco_ddr  |       1.350 |     0.311 |       0.309 |      0.002 |       NA    | Unspecified | NA         |
| Vcco_mio0 |       3.300 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vcco_mio1 |       1.800 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                            |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| Clock                                                                                      | Domain                                                                   | Constraint (ns) |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+
| clk_fpga_0                                                                                 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] |            10.0 |
| dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK        |            33.0 |
+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+---------------------------------------------+-----------+
| Name                                        | Power (W) |
+---------------------------------------------+-----------+
| c64pro_top                                  |     1.431 |
|   dbg_hub                                   |     0.003 |
|     inst                                    |     0.003 |
|       BSCANID.u_xsdbm_id                    |     0.003 |
|   u_ila_0                                   |     0.040 |
|     inst                                    |     0.040 |
|       ila_core_inst                         |     0.040 |
|   u_pl_top                                  |     0.082 |
|     u0_eeg_top                              |     0.005 |
|       transmit_arrange[0].u_ads1299_arrange |     0.001 |
|       u_eeg_upload                          |     0.001 |
|     u0_upload_top                           |     0.033 |
|       u_upload_config                       |     0.015 |
|       u_upload_protocol_intan               |     0.003 |
|       u_upload_protocol_ql                  |     0.004 |
|       u_upload_sort                         |     0.010 |
|     u1_eeg_top                              |     0.002 |
|     u1_upload_top                           |     0.029 |
|       u_upload_config                       |     0.012 |
|       u_upload_protocol_intan               |     0.003 |
|       u_upload_protocol_ql                  |     0.004 |
|       u_upload_sort                         |     0.009 |
|     u_cur_mon_top                           |     0.010 |
|       u0_fifo_generator_1                   |     0.002 |
|       u_cur_mon_config                      |     0.002 |
|       u_cur_monitor                         |     0.001 |
|       u_vio_cur_flt_state                   |     0.002 |
|     u_eeg_emg_upload                        |     0.003 |
|       u0_fifo_generator_0                   |     0.003 |
|   u_ps_a9_1                                 |     1.304 |
|     design_a9_1_i                           |     1.298 |
|       CUR_SPI                               |     0.004 |
|       STIM_SPI                              |     0.004 |
|       ZCHECK_SPI                            |     0.004 |
|       axi_dma_0                             |     0.002 |
|       axi_dma_1                             |     0.005 |
|       axi_dma_2                             |     0.005 |
|       axi_dma_3                             |     0.005 |
|       axi_smc                               |     0.020 |
|       axis_data_fifo_1                      |     0.001 |
|       axis_data_fifo_2                      |     0.012 |
|       axis_data_fifo_3                      |     0.033 |
|       processing_system7_0                  |     1.175 |
|       smartconnect_0                        |     0.025 |
+---------------------------------------------+-----------+