Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Date : Fri Sep 4 15:41:38 2026 | Host : DESKTOP-VN054CM running 64-bit major release (build 9200) | Command : report_clock_utilization -file c64pro_top_clock_utilization_routed.rpt | Design : c64pro_top | Device : 7z020-clg400 | Speed File : -2 PRODUCTION 1.12 2019-11-22 | Design State : Routed --------------------------------------------------------------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 6. Device Cell Placement Summary for Global Clock g0 7. Device Cell Placement Summary for Global Clock g1 8. Clock Region Cell Placement per Global Clock: Region X0Y0 9. Clock Region Cell Placement per Global Clock: Region X1Y0 10. Clock Region Cell Placement per Global Clock: Region X0Y1 11. Clock Region Cell Placement per Global Clock: Region X1Y1 12. Clock Region Cell Placement per Global Clock: Region X0Y2 13. Clock Region Cell Placement per Global Clock: Region X1Y2 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 2 | 32 | 0 | 0 | 0 | | BUFH | 0 | 72 | 0 | 0 | 0 | | BUFIO | 0 | 16 | 0 | 0 | 0 | | BUFMR | 0 | 8 | 0 | 0 | 0 | | BUFR | 0 | 16 | 0 | 0 | 0 | | MMCM | 0 | 4 | 0 | 0 | 0 | | PLL | 0 | 4 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 6 | 34979 | 0 | 10.000 | clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 2 | 465 | 0 | 33.000 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | +-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+--------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+-------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads 3. Global Clock Source Details ------------------------------ +-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+ | src0 | g0 | PS7/FCLKCLK[0] | PS7_X0Y0 | PS7_X0Y0 | X0Y2 | 1 | 0 | 10.000 | clk_fpga_0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] | | src1 | g1 | BSCANE2/TCK | None | BSCAN_X0Y0 | X1Y1 | 1 | 0 | 33.000 | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TCK | +-----------+-----------+-----------------+------------+------------+--------------+-------------+-----------------+---------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 50 | 1 | 50 | 7382 | 2500 | 3341 | 1000 | 1 | 60 | 26 | 30 | 0 | 60 | | X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 9171 | 3200 | 3020 | 850 | 0 | 60 | 27 | 30 | 0 | 40 | | X0Y1 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3726 | 1200 | 1504 | 400 | 0 | 20 | 9 | 10 | 0 | 20 | | X1Y1 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 50 | 1 | 50 | 7441 | 2600 | 2471 | 850 | 0 | 60 | 19 | 30 | 0 | 40 | | X0Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1865 | 1200 | 662 | 400 | 0 | 20 | 9 | 10 | 0 | 20 | | X1Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 2 | 50 | 1 | 50 | 4218 | 2600 | 1386 | 850 | 0 | 60 | 12 | 30 | 0 | 40 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y2 | 0 | 0 | | Y1 | 0 | 0 | | Y0 | 0 | 0 | +----+----+----+ 6. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------+ | g0 | BUFG/O | n/a | clk_fpga_0 | 10.000 | {0.000 5.000} | 34396 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+-------------------------------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+-------+-------+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+-------+-------+-----------------------+ | Y2 | 1875 | 4233 | 0 | | Y1 | 3880 | 7122 | 0 | | Y0 | 7665 | 9621 | 0 | +----+-------+-------+-----------------------+ 7. Device Cell Placement Summary for Global Clock g1 ---------------------------------------------------- +-----------+-----------------+-------------------+--------------------------------------------------------------------------------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+--------------------------------------------------------------------------------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------+ | g1 | BUFG/O | n/a | dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK | 33.000 | {0.000 16.500} | 462 | 0 | 0 | 0 | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | +-----------+-----------------+-------------------+--------------------------------------------------------------------------------------------+-------------+----------------+-------------+----------+----------------+----------+----------------------------------------+ * Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+------+-----------------------+ | | X0 | X1 | HORIZONTAL PROG DELAY | +----+----+------+-----------------------+ | Y2 | 0 | 0 | - | | Y1 | 0 | 339 | 0 | | Y0 | 0 | 123 | 0 | +----+----+------+-----------------------+ 8. Clock Region Cell Placement per Global Clock: Region X0Y0 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 7665 | 0 | 7382 | 255 | 27 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 9. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 9621 | 0 | 9048 | 544 | 27 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | g1 | n/a | BUFG/O | None | 123 | 0 | 123 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 10. Clock Region Cell Placement per Global Clock: Region X0Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 3880 | 0 | 3726 | 144 | 9 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 11. Clock Region Cell Placement per Global Clock: Region X1Y1 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 7122 | 0 | 7102 | 0 | 19 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | | g1 | n/a | BUFG/O | None | 339 | 0 | 339 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 12. Clock Region Cell Placement per Global Clock: Region X0Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 1875 | 0 | 1865 | 0 | 9 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts 13. Clock Region Cell Placement per Global Clock: Region X1Y2 ------------------------------------------------------------- +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ | g0 | n/a | BUFG/O | None | 4233 | 0 | 4218 | 3 | 12 | 0 | 0 | 0 | 0 | 0 | u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------------------------------------------------+ * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered ** Non-Clock Loads column represents cell count of non-clock pin loads *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y16 [get_cells u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG] set_property LOC BUFGCTRL_X0Y0 [get_cells dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck] # Location of IO Primitives which is load of clock spine # Location of clock ports # Clock net "u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0" driven by instance "u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG" located at site "BUFGCTRL_X0Y16" #startgroup create_pblock {CLKAG_u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0} add_cells_to_pblock [get_pblocks {CLKAG_u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0}]]] resize_pblock [get_pblocks {CLKAG_u_ps_a9_1/design_a9_1_i/processing_system7_0/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X0Y2:CLOCKREGION_X0Y2 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1 CLOCKREGION_X1Y2:CLOCKREGION_X1Y2} #endgroup # Clock net "dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i" driven by instance "dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i} add_cells_to_pblock [get_pblocks {CLKAG_dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i}]]] resize_pblock [get_pblocks {CLKAG_dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} #endgroup