xilinx.com ipcache 9844d9e666fa20e5 0 clk_wiz_0 100000000 100000000 MMCM false empty cddcdone cddcreq clkfb_in_n clkfb_in clkfb_in_p SINGLE clkfb_out_n clkfb_out clkfb_out_p clkfb_stopped 100.0 0.010 100.0 0.010 BUFG 218.754 false 98.575 50.000 8 0.000 1 true BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false BUFG 0.0 false 0.0 50.000 100.000 0.000 1 false 600.000 Custom Custom clk_in_sel clk_out1 false clk_out2 false clk_out3 false clk_out4 false clk_out5 false clk_out6 false clk_out7 false CLK_VALID auto clk_wiz_0 daddr dclk den Custom Custom din dout drdy dwe false false false false false false false false false FDBK_AUTO input_clk_stopped frequency Enable_AXI Units_MHz Units_UI UI No_Jitter locked OPTIMIZED 10.000 0.000 false 10.000 10.000 125.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false ZHOLD 1 None 0.010 0.010 false 1 false false false WAVEFORM false UNKNOWN OPTIMIZED 4 0.000 10.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 CLKFBOUT SYSTEM_SYNCHRONOUS 1 None 0.010 power_down 1 clk_in1 MMCM mmcm_adv 100.000 0.010 10.000 Single_ended_clock_capable_pin psclk psdone psen psincdec 100.0 REL_PRIMARY Custom reset ACTIVE_HIGH 100.000 0.010 10.000 clk_in2 Single_ended_clock_capable_pin CENTER_HIGH 250 0.004 STATUS empty 100.0 100.0 100.0 100.0 false false false false false false false true false false true false false false true false true false false false zynq xc7z020 clg400 VERILOG -2 4e5828b5 9844d9e666fa20e5 clk_wiz_0 $Change: 3850373 $ 984cb417 45 IP_Unknown 12 TRUE . . 2023.1 GLOBAL