`timescale 1ns/1ps
 
module pl_top_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	localparam	T_CLK 				= 10	;		//ns

	localparam	RSH2116_QTY			= 4		;

	localparam	EEG_ADS1299_QTY		= 8		;
	localparam	EEG_ADS1299_SPI_QTY	= 4		;
	
	//eeg ads1299
	localparam 	EEG_BRAM_ADDR_TEST_RO			= 13'h0000;
	localparam 	EEG_BRAM_ADDR_TEST_RW			= 13'h0004;
	
	localparam 	EEG_BRAM_ADDR_EEG_ER			= 13'h0040;
	localparam 	EEG_BRAM_ADDR_EEG_CR			= 13'h0044;
	localparam 	EEG_BRAM_ADDR_EEG_SR			= 13'h0048;
	localparam 	EEG_BRAM_ADDR_EEG_TR			= 13'h0100;
	localparam 	EEG_BRAM_ADDR_EEG_RR			= 13'h0200;
	
	localparam 	EEG_BRAM_ADDR_EEG_TR_MASK		= 13'h1F00;
	localparam 	EEG_BRAM_ADDR_EEG_RR_MASK		= 13'h1F00;
	
	//rhs2116
	parameter	CMD_CNV				= 2'b00;
	parameter	CMD_STIM			= 2'b01;
	parameter	CMD_NULL			= 2'b01;
	parameter	CMD_END				= 2'b01;
	parameter	CMD_WRITE			= 2'b10;
	parameter	CMD_READ			= 2'b11;
	
	parameter	STIM_POL_REG_ADDR	= 8'd44;
	parameter	POS_CUR_REG_ADDR	= 8'd96;
	parameter	NEG_CUR_REG_ADDR	= 8'd64;
	
	
	localparam 	BRAM_ADDR_TEST_RW				= 13'h0000;
	localparam 	BRAM_ADDR_TEST_RO_DATA			= 13'h0004;
	localparam 	BRAM_ADDR_TEST_VERSION			= 13'h0008;
	
	localparam 	BRAM_ADDR_UPDATE_PERIOD			= 13'h0020;
	localparam 	BRAM_ADDR_UPLOAD_ROUND_NUM		= 13'h0024;
	localparam 	BRAM_ADDR_ENABLE				= 13'h0028;
	localparam 	BRAM_ADDR_RESET					= 13'h002C;
	localparam 	BRAM_ADDR_DDS_PHASE_TRIG		= 13'h0030;
	localparam 	BRAM_ADDR_SWITCH_CTRL			= 13'h0034;
	localparam 	BRAM_ADDR_SWITCH_DATA0			= 13'h0040;
	localparam 	BRAM_ADDR_SWITCH_DATA1			= 13'h0044;
	localparam	BRAM_ADDR_UPLOAD_TIMEOUT		= 13'h0048;
	
	localparam 	BRAM_ADDR_SPI_STATE_START		= 13'h0100;
	localparam 	BRAM_ADDR_SPI_TX_START			= 13'h0180;
	localparam 	BRAM_ADDR_SPI_RX_START			= 13'h0200;
	localparam 	BRAM_ADDR_SPI_ERR_START			= 13'h0280;
	
	
	localparam 	BRAM_ADDR_DDS_PHASE_INC_START	= 13'h0400;
	localparam 	BRAM_ADDR_DDS_PHASE_OFF_START	= 13'h0480;
	
	localparam 	BRAM_ADDR_CHIP_0_CNV_CMD_LTH	= 13'h0500;
	localparam 	BRAM_ADDR_CHIP_1_CNV_CMD_LTH	= 13'h0504;
	localparam 	BRAM_ADDR_CHIP_2_CNV_CMD_LTH	= 13'h0508;
	localparam 	BRAM_ADDR_CHIP_3_CNV_CMD_LTH	= 13'h050C;
	
	localparam 	BRAM_ADDR_STIM_TRIM_P_MASK		= 13'h1F00;
	localparam 	BRAM_ADDR_STIM_TRIM_P_START		= 13'h0600;
	
	localparam 	BRAM_ADDR_STIM_TRIM_N_MASK		= 13'h1F00;
	localparam 	BRAM_ADDR_STIM_TRIM_N_START		= 13'h0700;
	
	localparam 	BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_P	= 13'h0600;
	localparam 	BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_P	= 13'h0610;
	localparam 	BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_P	= 13'h0620;
	localparam 	BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_P	= 13'h0630;
	
	localparam 	BRAM_ADDR_CHIP_0_STIM_CH_0_3_TRIM_N	= 13'h0700;
	localparam 	BRAM_ADDR_CHIP_1_STIM_CH_0_3_TRIM_N	= 13'h0710;
	localparam 	BRAM_ADDR_CHIP_2_STIM_CH_0_3_TRIM_N	= 13'h0720;
	localparam 	BRAM_ADDR_CHIP_3_STIM_CH_0_3_TRIM_N	= 13'h0730;
	
	localparam 	BRAM_ADDR_CHIP_0_CNV_CMD_START	= 13'h1000;
	localparam 	BRAM_ADDR_CHIP_1_CNV_CMD_START	= 13'h1040;
	localparam 	BRAM_ADDR_CHIP_2_CNV_CMD_START	= 13'h1080;
	localparam 	BRAM_ADDR_CHIP_3_CNV_CMD_START	= 13'h10C0;
	
	localparam 	COVER_Y	= 1'b1;
	localparam 	COVER_N	= 1'b0;
	
	localparam 	STAGE_SS	= 4'h1;
	localparam 	STAGE_RE	= 4'h3;
	localparam 	STAGE_FS	= 4'h4;
	localparam 	STAGE_EE	= 4'h2;
	
	localparam 	CHIP_0	= 4'h0;
	localparam 	CHIP_1	= 4'h1;
	localparam 	CHIP_2	= 4'h2;
	localparam 	CHIP_3	= 4'h3;
	
	localparam 	CHANNEL_0	= 0;
	localparam 	CHANNEL_1	= 1;
	localparam 	CHANNEL_2	= 2;
	localparam 	CHANNEL_3	= 3;
	localparam 	CHANNEL_4	= 4;
	localparam 	CHANNEL_5	= 5;
	localparam 	CHANNEL_6	= 6;
	localparam 	CHANNEL_7	= 7;
	localparam 	CHANNEL_8	= 8;
	localparam 	CHANNEL_9	= 9;
	localparam 	CHANNEL_A	= 10;
	localparam 	CHANNEL_B	= 11;
	localparam 	CHANNEL_C	= 12;
	localparam 	CHANNEL_D	= 13;
	localparam 	CHANNEL_E	= 14;
	localparam 	CHANNEL_F	= 15;
	
	localparam 	DDS_CH_0	= 0;
	localparam 	DDS_CH_1	= 1;
	localparam 	DDS_CH_2	= 2;
	localparam 	DDS_CH_3	= 3;
	localparam 	DDS_CH_4	= 4;
	localparam 	DDS_CH_5	= 5;
	localparam 	DDS_CH_6	= 6;
	localparam 	DDS_CH_7	= 7;
	localparam 	DDS_CH_8	= 8;
	localparam 	DDS_CH_9	= 9;
	localparam 	DDS_CH_A	= 10;
	localparam 	DDS_CH_B	= 11;
	localparam 	DDS_CH_C	= 12;
	localparam 	DDS_CH_D	= 13;
	localparam 	DDS_CH_E	= 14;
	localparam 	DDS_CH_F	= 15;
	
	localparam 	GAIN_MAX	= 9'h100;

	//Message Config
	localparam 	BRAM_ADDR_MSG_TEST_RO			= 13'h0000;
	localparam 	BRAM_ADDR_MSG_TEST_RW			= 13'h0004;
	localparam 	BRAM_ADDR_MSG_SEL_EEG24			= 13'h0010;
	localparam 	BRAM_ADDR_MSG_ROUNDS_QTY		= 13'h0014;
	localparam 	BRAM_ADDR_MSG_PRE_MSG_LTH		= 13'h0018;
	localparam 	BRAM_ADDR_MSG_PRE_MSG_START		= 13'h0100;
	localparam 	BRAM_ADDR_MSG_CH_MAP_START		= 13'h0200;
	localparam 	BRAM_ADDR_MSG_UPLOAD_CH_START	= 13'h0300;

	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg								clk						;
	reg								rst_n					;
	
	reg		[13-1:0]				bram_stim_addr			;
	reg								bram_stim_clk			;
	reg		[32-1:0]				bram_stim_din			;
	wire	[32-1:0]				bram_stim_dout			;
	reg								bram_stim_en			;
	reg								bram_stim_rst			;
	reg		[ 4-1:0]				bram_stim_we			;
	
	reg		[13-1:0]				bram_eeg_addr			;
	reg								bram_eeg_clk			;
	reg		[32-1:0]				bram_eeg_din			;
	wire	[32-1:0]				bram_eeg_dout			;
	reg								bram_eeg_en				;
	reg								bram_eeg_rst			;
	reg		[ 4-1:0]				bram_eeg_we				;
	
	reg		[13-1:0]				bram_emg_addr			;
	reg								bram_emg_clk			;
	reg		[32-1:0]				bram_emg_din			;
	wire	[32-1:0]				bram_emg_dout			;
	reg								bram_emg_en				;
	reg								bram_emg_rst			;
	reg		[ 4-1:0]				bram_emg_we				;
	
	reg		[13-1:0]				bram_accel_addr			;
	reg								bram_accel_clk			;
	reg		[32-1:0]				bram_accel_din			;
	wire	[32-1:0]				bram_accel_dout			;
	reg								bram_accel_en			;
	reg								bram_accel_rst			;
	reg		[ 4-1:0]				bram_accel_we			;
	
	reg		[13-1:0]				bram_msg_addr			;
	reg								bram_msg_clk			;
	reg		[32-1:0]				bram_msg_din			;
	wire	[32-1:0]				bram_msg_dout			;
	reg								bram_msg_en				;
	reg								bram_msg_rst			;
	reg		[ 4-1:0]				bram_msg_we				;
	
	wire							stim_int				;
	wire							eeg_int					;
	wire							emg_int					;
	wire							accel_int				;
        
	wire	[32-1:0]				m_axis_stim_tdata		;
	wire							m_axis_stim_tlast		;
	wire							m_axis_stim_tready		;
	wire							m_axis_stim_tvalid		;

	reg								m_axis_record_tfull		;
	wire	[ 8-1:0]				m_axis_record_tdata		;
	wire	[ 1-1:0]				m_axis_record_tkeep		;
	wire							m_axis_record_tlast		;
	reg								m_axis_record_tready	;
	wire							m_axis_record_tvalid	;
	
	//---------------------------------------------	RSH2116
	wire	[RSH2116_QTY-1:0]		rsh2116_enable			;
	wire	[RSH2116_QTY-1:0]		rsh2116_spi_cs			;
	wire	[RSH2116_QTY-1:0]		rsh2116_spi_sclk		;
	wire	[RSH2116_QTY-1:0]		rsh2116_spi_mosi		;
	wire	[RSH2116_QTY-1:0]		rsh2116_spi_miso		;

	//---------------------------------------------	ADS1299 for EEG
	wire	[    EEG_ADS1299_QTY-1:0]	eeg_ads1299_spi_cs	;
	wire	[EEG_ADS1299_SPI_QTY-1:0]	eeg_ads1299_spi_sclk;
	wire	[EEG_ADS1299_SPI_QTY-1:0]	eeg_ads1299_spi_mosi;
	wire	[EEG_ADS1299_SPI_QTY-1:0]	eeg_ads1299_spi_miso;
	wire	[EEG_ADS1299_SPI_QTY-1:0]	eeg_ads1299_drdy_n	;
	wire								eeg_ads1299_start	;

	//---------------------------------------------	ADS1299 for EMG
	wire							emg_ads1299_spi_cs		;
	wire							emg_ads1299_spi_sclk	;
	wire							emg_ads1299_spi_mosi	;
	reg								emg_ads1299_spi_miso	;
	reg								emg_ads1299_drdy_n		;
	wire							emg_ads1299_start		;
	wire							emg_ads1299_reset_n		;
	wire							emg_ads1299_pwdn_n		;
	
	//---------------------------------------------	Accel
	wire							accel_spi_cs			;
	wire							accel_spi_sclk			;
	wire							accel_spi_mosi			;
	reg								accel_spi_miso			;
	reg								accel_int0				;
	reg								accel_int1				;

	//---------------------------------------------	ADG1414
	wire							adg1414_spi_sync		;
	wire							adg1414_spi_sclk		;
	wire							adg1414_spi_mosi		;

	//---------------------------------------------	Trigger
	reg								trigger_reset			;
	reg		[32-1:0]				trigger_in				;
	wire	[32-1:0]				trigger_out				;

	//--------------------------------------------- FIFO: stim input
	reg		[31:0]					s_axis_tdata			;
	reg								s_axis_tlast			;
	wire							s_axis_tready			;
	reg								s_axis_tvalid			;

    wire	[EEG_ADS1299_QTY-1:0]	emg_ads1299_cs_w		;
    wire	[EEG_ADS1299_QTY-1:0]	emg_ads1299_sclk_w		;
    wire    [EEG_ADS1299_QTY-1:0]	emg_ads1299_mosi_w		;
    wire	[EEG_ADS1299_QTY-1:0]	emg_ads1299_miso_w		;
    wire	[EEG_ADS1299_QTY-1:0]	emg_ads1299_drdy_w		;
    wire	[EEG_ADS1299_QTY-1:0]	emg_ads1299_start_w		;

	
	reg								no_enable				;

	reg		[32-1:0]				temp32					;

	reg		[32-1:0]				msg_byte_cnt			;
	reg								msg_head_valid			;
	
	integer		n;
	genvar		i;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	axis_data_fifo_w32_d32 u_axis_stream_data_fifo_rs
		(
			.s_axis_aclk			( clk 					),
			.s_axis_aresetn			( rst_n					),
			
			.s_axis_tvalid			( s_axis_tvalid			),
			.s_axis_tready			( s_axis_tready			),
			.s_axis_tdata			( s_axis_tdata			),
			.s_axis_tlast			( s_axis_tlast			),
			
			.m_axis_tvalid			( m_axis_stim_tvalid	),
			.m_axis_tready			( m_axis_stim_tready	),
			.m_axis_tdata			( m_axis_stim_tdata		),
			.m_axis_tlast			( m_axis_stim_tlast		)
		);
	
	pl_top# 
		(
			.CLK_FREQ				( 100					),
			.CLK_PERIOD				( T_CLK					)
		)
	DUT
		(
			.clk					( clk					),
			.rst_n					( rst_n					),

			.bram_stim_addr			( bram_stim_addr		),
			.bram_stim_clk			( bram_stim_clk			),
			.bram_stim_din			( bram_stim_din			),
			.bram_stim_dout			( bram_stim_dout		),
			.bram_stim_en			( bram_stim_en			),
			.bram_stim_rst			( bram_stim_rst			),
			.bram_stim_we			( bram_stim_we			),
			
			.bram_eeg_addr			( bram_eeg_addr			),
			.bram_eeg_clk			( bram_eeg_clk			),
			.bram_eeg_din			( bram_eeg_din			),
			.bram_eeg_dout			( bram_eeg_dout			),
			.bram_eeg_en			( bram_eeg_en			),
			.bram_eeg_rst			( bram_eeg_rst			),
			.bram_eeg_we			( bram_eeg_we			),
			
			.bram_emg_addr			( bram_emg_addr			),
			.bram_emg_clk			( bram_emg_clk			),
			.bram_emg_din			( bram_emg_din			),
			.bram_emg_dout			( bram_emg_dout			),
			.bram_emg_en			( bram_emg_en			),
			.bram_emg_rst			( bram_emg_rst			),
			.bram_emg_we			( bram_emg_we			),
			
			.bram_accel_addr		( bram_accel_addr		),
			.bram_accel_clk			( bram_accel_clk		),
			.bram_accel_din			( bram_accel_din		),
			.bram_accel_dout		( bram_accel_dout		),
			.bram_accel_en			( bram_accel_en			),
			.bram_accel_rst			( bram_accel_rst		),
			.bram_accel_we			( bram_accel_we			),
			
			.bram_msg_addr			( bram_msg_addr			),
			.bram_msg_clk			( bram_msg_clk			),
			.bram_msg_din			( bram_msg_din			),
			.bram_msg_dout			( bram_msg_dout			),
			.bram_msg_en			( bram_msg_en			),
			.bram_msg_rst			( bram_msg_rst			),
			.bram_msg_we			( bram_msg_we			),
			
			.stim_int				( stim_int				),
			.eeg_int				( eeg_int				),
			.emg_int				( emg_int				),
			.accel_int				( accel_int				),
			
			//------------------------------------------ FIFO: stim input and record output
			.m_axis_stim_tdata		( m_axis_stim_tdata		),
			.m_axis_stim_tlast		( m_axis_stim_tlast		),
			.m_axis_stim_tready		( m_axis_stim_tready	),
			.m_axis_stim_tvalid		( m_axis_stim_tvalid	),
			
			.m_axis_record_tfull	( m_axis_record_tfull	),
			.m_axis_record_tdata	( m_axis_record_tdata	),
			.m_axis_record_tkeep	( m_axis_record_tkeep	),
			.m_axis_record_tlast	( m_axis_record_tlast	),
			.m_axis_record_tready	( m_axis_record_tready	),
			.m_axis_record_tvalid	( m_axis_record_tvalid	),
			
			//------------------------------------------ device: RHS2116
			.rsh2116_enable			( rsh2116_enable		),
			.rsh2116_spi_cs			( rsh2116_spi_cs		),
			.rsh2116_spi_sclk		( rsh2116_spi_sclk		),
			.rsh2116_spi_mosi		( rsh2116_spi_mosi		),
			.rsh2116_spi_miso		( rsh2116_spi_miso		),
			
			//------------------------------------------ device: ads1299
			.eeg_ads1299_spi_cs		( eeg_ads1299_spi_cs	),
			.eeg_ads1299_spi_sclk	( eeg_ads1299_spi_sclk	),
			.eeg_ads1299_spi_mosi	( eeg_ads1299_spi_mosi	),
			.eeg_ads1299_spi_miso	( eeg_ads1299_spi_miso	),
			.eeg_ads1299_drdy_n		( eeg_ads1299_drdy_n	),
			.eeg_ads1299_start		( eeg_ads1299_start		),
			
			//------------------------------------------ device: ads1299
			.emg_ads1299_spi_cs		( emg_ads1299_spi_cs	),
			.emg_ads1299_spi_sclk	( emg_ads1299_spi_sclk	),
			.emg_ads1299_spi_mosi	( emg_ads1299_spi_mosi	),
			.emg_ads1299_spi_miso	( emg_ads1299_spi_miso	),
			.emg_ads1299_drdy_n		( emg_ads1299_drdy_n	),
			.emg_ads1299_start		( emg_ads1299_start		),
			.emg_ads1299_reset_n	( emg_ads1299_reset_n	),
			.emg_ads1299_pwdn_n		( emg_ads1299_pwdn_n	),

			//------------------------------------------ device: MEMS
			.accel_spi_cs			( accel_spi_cs			),
			.accel_spi_sclk			( accel_spi_sclk		),
			.accel_spi_mosi			( accel_spi_mosi		),
			.accel_spi_miso			( accel_spi_miso		),
			.accel_int0				( accel_int0			),
			.accel_int1				( accel_int1			),

			//------------------------------------------	ADG1414
			.adg1414_spi_sync		( adg1414_spi_sync		),
			.adg1414_spi_sclk		( adg1414_spi_sclk		),
			.adg1414_spi_mosi		( adg1414_spi_mosi		),
			.adg1414_spi_miso		( 1'b0					),

			//------------------------------------------ Trigger
			.trigger_reset			( trigger_reset			),
			.trigger_in				( trigger_in			),
			.trigger_out			( trigger_out			),

			//------------------------------------------ Debug
			.debug_sig				( 						)
		);
	
	generate
		for(i=0; i<RSH2116_QTY; i=i+1) begin : rhs2116
			rhs2116_mod u_rhs2116_mod
				(
					.cs			( rsh2116_spi_cs[i]			),
					.sclk		( rsh2116_spi_sclk[i]		),
					.mosi		( rsh2116_spi_mosi[i]		),
					.miso		( rsh2116_spi_miso[i]		)
				);
		end
	endgenerate
	
	generate
		for(i=0; i<EEG_ADS1299_QTY; i=i+1) begin : ADS1299_EEG
			ads1299_mod u_ads1299_mod
				(
					.cs			( emg_ads1299_cs_w[i]		),
					.sclk		( emg_ads1299_sclk_w[i]		),
					.mosi		( emg_ads1299_mosi_w[i]		),
					.miso		( emg_ads1299_miso_w[i]		),
					.drdy		( emg_ads1299_drdy_w[i]		),
					.start		( emg_ads1299_start_w[i]	)
				);
		end
	endgenerate
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk				<= 1'b0	;
			rst_n			<= 1'b0	;

			//bram
			bram_stim_addr	<= 0	;
			bram_stim_din	<= 0	;
			bram_stim_en	<= 0	;
			bram_stim_rst	<= 0	;
			bram_stim_we	<= 0	;

			bram_eeg_addr	<= 0	;
			bram_eeg_din	<= 0	;
			bram_eeg_en		<= 0	;
			bram_eeg_rst	<= 0	;
			bram_eeg_we		<= 0	;

			bram_emg_addr	<= 0	;
			bram_emg_din	<= 0	;
			bram_emg_en		<= 0	;
			bram_emg_rst	<= 0	;
			bram_emg_we		<= 0	;

			bram_accel_addr	<= 0	;
			bram_accel_din	<= 0	;
			bram_accel_en	<= 0	;
			bram_accel_rst	<= 0	;
			bram_accel_we	<= 0	;

			bram_msg_addr	<= 0	;
			bram_msg_din	<= 0	;
			bram_msg_en		<= 0	;
			bram_msg_rst	<= 0	;
			bram_msg_we		<= 0	;

			
			accel_spi_miso	<= 1'b0	;
			accel_int0		<= 1'b0	;
			accel_int1		<= 1'b0	;

			//FIFO
			m_axis_record_tfull<= 1'b0;

			s_axis_tdata	<= 0	;
			s_axis_tlast	<= 1'b0	;
			s_axis_tvalid	<= 1'b0	;

			m_axis_record_tready<= 1'b1;

			//Trigger
			trigger_reset	<= 1'b0;
			trigger_in		<= 0;
		
			no_enable		<= 1'b1;
		end
	endtask
	
	task write_bram_2116;
		input [12:0] addr;
		input [31:0] data;
		begin
			@ ( posedge clk );
			bram_stim_addr	<= addr;
			bram_stim_din	<= data;
			bram_stim_en	<= 1'b1;
			bram_stim_we	<= 4'hF;
			@ ( posedge clk );
			bram_stim_en	<= 1'b0;
			bram_stim_we	<= 4'h0;
		end
	endtask
	
	task read_bram_2116;
		input [12:0] addr;
		output [31:0] data;
		begin
			@ ( posedge clk );
			bram_stim_addr	<= addr;
			bram_stim_en	<= 1'b1;
			bram_stim_we	<= 4'h0;
			@ ( posedge clk );
			bram_stim_en	<= 1'b0;
			@ ( posedge clk );
			data <= bram_stim_dout;
		end
	endtask
	
	task write_bram_eeg;
		input [12:0] addr;
		input [31:0] data;
		begin
			@ ( posedge clk );
			bram_eeg_addr	<= addr;
			bram_eeg_din	<= data;
			bram_eeg_en		<= 1'b1;
			bram_eeg_we		<= 4'hF;
			@ ( posedge clk );
			bram_eeg_en		<= 1'b0;
			bram_eeg_we		<= 4'h0;
		end
	endtask
	
	task read_bram_eeg;
		input [12:0] addr;
		output [31:0] data;
		begin
			@ ( posedge clk );
			bram_eeg_addr	<= addr;
			bram_eeg_en		<= 1'b1;
			bram_eeg_we		<= 4'h0;
			@ ( posedge clk );
			bram_eeg_en		<= 1'b0;
			@ ( posedge clk );
			data <= bram_eeg_dout;
		end
	endtask
	
	task write_bram_emg;
		input [12:0] addr;
		input [31:0] data;
		begin
			@ ( posedge clk );
			bram_emg_addr	<= addr;
			bram_emg_din	<= data;
			bram_emg_en		<= 1'b1;
			bram_emg_we		<= 4'hF;
			@ ( posedge clk );
			bram_emg_en		<= 1'b0;
			bram_emg_we		<= 4'h0;
		end
	endtask
	
	task read_bram_emg;
		input [12:0] addr;
		output [31:0] data;
		begin
			@ ( posedge clk );
			bram_emg_addr	<= addr;
			bram_emg_en		<= 1'b1;
			bram_emg_we		<= 4'h0;
			@ ( posedge clk );
			bram_emg_en		<= 1'b0;
			@ ( posedge clk );
			data <= bram_emg_dout;
		end
	endtask
	
	task write_bram_msg;
		input [12:0] addr;
		input [31:0] data;
		begin
			@ ( posedge clk );
			bram_msg_addr	<= addr;
			bram_msg_din	<= data;
			bram_msg_en		<= 1'b1;
			bram_msg_we		<= 4'hF;
			@ ( posedge clk );
			bram_msg_en		<= 1'b0;
			bram_msg_we		<= 4'h0;
		end
	endtask
	
	task write_bram_byte_msg;
		input [12:0] addr;
		input [ 7:0] data;

		reg [31:0] data_w;
		reg [ 3:0] we_w;
		begin
			we_w[0] <= (addr[1:0]==2'b00)? 1'b1:1'b0;
			we_w[1] <= (addr[1:0]==2'b01)? 1'b1:1'b0;
			we_w[2] <= (addr[1:0]==2'b10)? 1'b1:1'b0;
			we_w[3] <= (addr[1:0]==2'b11)? 1'b1:1'b0;
			
			data_w[ 7: 0] <= (addr[1:0]==2'b00)? data:8'h00;
			data_w[15: 8] <= (addr[1:0]==2'b01)? data:8'h00;
			data_w[23:16] <= (addr[1:0]==2'b10)? data:8'h00;
			data_w[31:24] <= (addr[1:0]==2'b11)? data:8'h00;

			@ ( posedge clk );
			bram_msg_addr	<= addr;
			bram_msg_din	<= data_w;
			bram_msg_en		<= 1'b1;
			bram_msg_we		<= we_w;
			@ ( posedge clk );
			bram_msg_en		<= 1'b0;
			bram_msg_we		<= 4'h0;
		end
	endtask
	
	task read_bram_msg;
		input [12:0] addr;
		output [31:0] data;
		begin
			@ ( posedge clk );
			bram_msg_addr	<= addr;
			bram_msg_en		<= 1'b1;
			bram_msg_we		<= 4'h0;
			@ ( posedge clk );
			bram_msg_en		<= 1'b0;
			@ ( posedge clk );
			data <= bram_msg_dout;
		end
	endtask
	
	task write_fifo;
		input [32-1:0]	tdata;
		input			tlast;
		begin
			s_axis_tdata	<= tdata;
			s_axis_tvalid	<= 1'b1;
			s_axis_tlast	<= tlast;
			@ ( posedge clk );
			while(~s_axis_tready) @ ( posedge clk );
			if(tlast) begin
				s_axis_tvalid	<= 1'b0;
				s_axis_tlast	<= 1'b0;
			end
		end
	endtask
	
	//*****************************************************************************
	// Function
	//*****************************************************************************
	function [32:0] code_null;
		input [4-1:0]	chip;
		code_null = {CMD_NULL, 2'b00, chip, 24'd0};
	endfunction

	function [32:0] code_cnv;
		input [4-1:0]	chip;
		input [6-1:0]	channel;
		code_cnv = {CMD_CNV, 4'd0, chip, channel, 16'd0};
	endfunction

	function [32:0] code_read;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		code_read = {CMD_READ, 2'b00, chip, reg_addr, 16'd0};
	endfunction

	function [32:0] code_read_u;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		code_read_u = {CMD_READ, 2'b10, chip, reg_addr, 16'd0};
	endfunction

	function [32:0] code_write;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		input [16-1:0]	data;
		code_write = {CMD_WRITE, 2'b00, chip, reg_addr, data};
	endfunction

	function [32:0] code_write_u;
		input [ 4-1:0]	chip;
		input [ 8-1:0]	reg_addr;
		input [16-1:0]	data;
		code_write_u = {CMD_WRITE, 2'b10, chip, reg_addr, data};
	endfunction

	function [32:0] code_stim_sine;
		input [4-1:0]	chip;
		input			cover;
		input [4-1:0]	stage;
		input [4-1:0]	channel;
		input [7-1:0]	dds_ch;
		input [9-1:0]	gain;
		code_stim_sine = {CMD_STIM, 1'b0, cover, chip, stage, channel, dds_ch, gain};
	endfunction

	function [32:0] code_end;
		input dds_en;
		input dds_rst;
		code_end = {CMD_END, 6'd0, 4'hF, 18'd0, dds_rst, dds_en};
	endfunction


	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	always @ ( * ) begin
		while(1) begin
			#99_333;
			trigger_in <= trigger_in + 1'b1;
		end
	end
	
//	always #( 600_000 )  m_axis_record_tfull = !m_axis_record_tfull;
	// always begin
	// 	#6_138_136;
	// 	m_axis_record_tfull <= 1'b1;
	// 	#10_000_000;
	// 	m_axis_record_tfull <= 1'b0;
	// 	#100_000_000;
	// end
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		#100

		//switch on
		write_bram_2116(BRAM_ADDR_SWITCH_CTRL, 32'h1);
		write_bram_2116(BRAM_ADDR_SWITCH_DATA0, 32'hFFFFFFFF);
	//	write_bram_2116(BRAM_ADDR_SWITCH_DATA1, 32'hFFFFFFFF);

		//record config
		read_bram_msg(BRAM_ADDR_MSG_TEST_RO,		temp32	);
		write_bram_msg(BRAM_ADDR_MSG_TEST_RW,		32'h1	);
		read_bram_msg(BRAM_ADDR_MSG_TEST_RW,		temp32	);
		
		write_bram_msg(BRAM_ADDR_MSG_SEL_EEG24,		32'b00	);
		write_bram_msg(BRAM_ADDR_MSG_ROUNDS_QTY,	32'd10	);
		write_bram_msg(BRAM_ADDR_MSG_PRE_MSG_LTH,	32'd77	);

		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h00,	8'h5A);	//16'hA55A
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h01,	8'hA5);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h02,	8'h01);	//device -> PC
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h03,	8'h39);	//device type
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h04,	8'h01);	//device ID: 32'04030201
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h05,	8'h02);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h06,	8'h03);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h07,	8'h04);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h08,	8'h10);	//message length
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h09,	8'h11);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0A,	8'h12);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0B,	8'h13);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0C,	8'h56);	//cmd: 16'h0456
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0D,	8'h04);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0E,	8'h00);	//run time(ms)
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h0F,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h10,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h11,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h12,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h13,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h14,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h15,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h16,	8'h00);	//result
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h17,	8'h00);	//package id
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h18,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h19,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1A,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1B,	8'hFF);	//upload channel
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1C,	8'hFF);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1D,	8'hFF);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1E,	8'hFF);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h1F,	8'hFF);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h20,	8'hFF);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h21,	8'hFF);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h22,	8'hFF);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h23,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h24,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h25,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h26,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h27,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h28,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h29,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2A,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2B,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2C,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2D,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2E,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h2F,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h30,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h31,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h32,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h33,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h34,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h35,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h36,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h37,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h38,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h39,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3A,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3B,	8'h00);	//OriRate
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3C,	8'h7D);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3D,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3E,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h3F,	8'h00);	//SampleRate
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h40,	8'h7D);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h41,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h42,	8'h00);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h43,	8'h01);	//SampleLen
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h44,	8'h02);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h45,	8'h03);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h46,	8'h04);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h47,	8'h18);	//resolution
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h48,	8'h00);	//filter flag
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h49,	8'h10);	//DataLen
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4A,	8'h20);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4B,	8'h30);
		write_bram_byte_msg(BRAM_ADDR_MSG_PRE_MSG_START+8'h4C,	8'h40);

		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd00,	8'd58);	//PL_ch-0 -> PC_ch-59
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd01,	8'd59);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd02,	8'd52);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd03,	8'd49);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd04,	8'd50);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd05,	8'd63);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd06,	8'd48);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd07,	8'd62);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd08,	8'd23);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd09,	8'd13);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd10,	8'd09);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd11,	8'd10);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd12,	8'd56);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd13,	8'd15);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd14,	8'd54);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd15,	8'd14);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd16,	8'd39);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd17,	8'd36);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd18,	8'd33);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd19,	8'd17);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd20,	8'd46);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd21,	8'd47);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd22,	8'd42);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd23,	8'd45);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd24,	8'd40);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd25,	8'd41);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd26,	8'd38);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd27,	8'd35);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd28,	8'd32);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd29,	8'd34);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd30,	8'd16);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd31,	8'd37);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd32,	8'd06);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd33,	8'd26);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd34,	8'd04);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd35,	8'd05);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd36,	8'd24);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd37,	8'd21);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd38,	8'd08);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd39,	8'd30);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd40,	8'd55);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd41,	8'd57);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd42,	8'd53);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd43,	8'd51);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd44,	8'd44);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd45,	8'd61);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd46,	8'd43);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd47,	8'd60);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd48,	8'd18);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd49,	8'd20);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd50,	8'd31);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd51,	8'd28);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd52,	8'd07);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd53,	8'd25);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd54,	8'd02);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd55,	8'd00);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd56,	8'd01);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd57,	8'd03);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd58,	8'd11);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd59,	8'd12);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd60,	8'd22);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd61,	8'd19);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd62,	8'd29);
		write_bram_byte_msg(BRAM_ADDR_MSG_CH_MAP_START+8'd63,	8'd27);	//PL_ch-63 -> PC_ch-28

		write_bram_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h0,	32'hFFFFFFFF);
		write_bram_msg(BRAM_ADDR_MSG_UPLOAD_CH_START+8'h4,	32'hFFFFFFFF);
		
		//record:(ads1299)
		// #1_000
        // @ ( posedge clk );
		// write_bram_eeg(EEG_BRAM_ADDR_EEG_CR, {1'b1, 15'd10, 16'd0});
		
		//stim:(rhs2116)
		#1_000
		//Config DDS
		write_bram_2116(BRAM_ADDR_DDS_PHASE_INC_START + 8'h00, 32'h000029F1);
		write_bram_2116(BRAM_ADDR_DDS_PHASE_OFF_START, 32'h0);
		write_bram_2116(BRAM_ADDR_DDS_PHASE_TRIG, 1);
		
		//Config update period
		write_bram_2116(BRAM_ADDR_UPDATE_PERIOD, 31250/T_CLK);
		write_bram_2116(BRAM_ADDR_UPLOAD_ROUND_NUM, 10);
		write_bram_2116(BRAM_ADDR_UPLOAD_TIMEOUT, 70);
		
		#100
		@ ( posedge clk );
		while(1) begin

			// write_fifo(code_stim_sine(CHIP_0, COVER_N, STAGE_SS, CHANNEL_0, DDS_CH_0, GAIN_MAX),	1'b0);
			// write_fifo(code_stim_sine(CHIP_0, COVER_N, STAGE_EE, CHANNEL_1, DDS_CH_0, GAIN_MAX),	1'b0);
			// write_fifo(code_write_u  (CHIP_0, 8'd44, 16'h00),										1'b0);
			// write_fifo(code_read	 (CHIP_0, 8'd40),												1'b0);

			// write_fifo(code_cnv		 (CHIP_1, CHANNEL_0),											1'b0);
			// write_fifo(code_cnv		 (CHIP_1, CHANNEL_1),											1'b0);
			// write_fifo(code_read	 (CHIP_1, 8'hFB),												1'b0);
			// write_fifo(code_read	 (CHIP_1, 8'hFC),												1'b0);

			// write_fifo(code_stim_sine(CHIP_2, COVER_N, STAGE_SS, CHANNEL_0, DDS_CH_0, GAIN_MAX),	1'b0);
			// write_fifo(code_cnv		 (CHIP_2, CHANNEL_1),											1'b0);
			// write_fifo(code_write_u  (CHIP_2, 8'd44, 16'h00),										1'b0);
			// write_fifo(code_read	 (CHIP_2, 8'd40),												1'b0);

			// write_fifo(code_null	 (CHIP_3),														1'b0);
			// write_fifo(code_null	 (CHIP_3),														1'b0);
			// write_fifo(code_null	 (CHIP_3),														1'b0);
			// write_fifo(code_null	 (CHIP_3),														1'b0);
			
			write_fifo(code_cnv		(CHIP_0, CHANNEL_0),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_1),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_2),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_3),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_4),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_5),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_6),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_7),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_8),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_9),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_A),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_B),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_C),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_D),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_E),											1'b0);
			write_fifo(code_cnv		(CHIP_0, CHANNEL_F),											1'b0);
			write_fifo(code_read	(CHIP_0, 8'hFB),												1'b0);
			write_fifo(code_read	(CHIP_0, 8'hFC),												1'b0);

			write_fifo(code_cnv		(CHIP_1, CHANNEL_0),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_1),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_2),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_3),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_4),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_5),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_6),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_7),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_8),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_9),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_A),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_B),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_C),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_D),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_E),											1'b0);
			write_fifo(code_cnv		(CHIP_1, CHANNEL_F),											1'b0);
			write_fifo(code_read	(CHIP_1, 8'hFB),												1'b0);
			write_fifo(code_read	(CHIP_1, 8'hFC),												1'b0);

			write_fifo(code_cnv		(CHIP_2, CHANNEL_0),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_1),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_2),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_3),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_4),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_5),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_6),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_7),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_8),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_9),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_A),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_B),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_C),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_D),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_E),											1'b0);
			write_fifo(code_cnv		(CHIP_2, CHANNEL_F),											1'b0);
			write_fifo(code_read	(CHIP_2, 8'hFB),												1'b0);
			write_fifo(code_read	(CHIP_2, 8'hFC),												1'b0);

			write_fifo(code_cnv		(CHIP_3, CHANNEL_0),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_1),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_2),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_3),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_4),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_5),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_6),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_7),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_8),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_9),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_A),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_B),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_C),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_D),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_E),											1'b0);
			write_fifo(code_cnv		(CHIP_3, CHANNEL_F),											1'b0);
			write_fifo(code_read	(CHIP_3, 8'hFB),												1'b0);
			write_fifo(code_read	(CHIP_3, 8'hFC),												1'b0);

			write_fifo(code_end		(0, 0),															1'b1);

			// //if has stim
			// @ ( posedge clk );
			// if (no_enable) begin
			// 	no_enable <= 1'b0;
			// 	write_fifo(code_end	(1, 1),															1'b1);
			// end else
			// 	write_fifo(code_end	(1, 0),															1'b1);
		end
		
		// $stop;
		
	end

	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			msg_byte_cnt <= 0;
		else if ( m_axis_record_tvalid && m_axis_record_tready && m_axis_record_tlast )
			msg_byte_cnt <= 0;
		else if ( m_axis_record_tvalid && m_axis_record_tready )
			msg_byte_cnt <= msg_byte_cnt + 1'b1;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			msg_head_valid <= 1'b0;
		else if ( m_axis_record_tvalid && m_axis_record_tready && m_axis_record_tlast )
			msg_head_valid <= 1'b0;
		else if ( m_axis_record_tvalid && m_axis_record_tready && msg_byte_cnt == 0 )
			msg_head_valid <= (m_axis_record_tdata == 8'h5A)? 1'b1:1'b0;
	end
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	generate
		for(i=0;i<EEG_ADS1299_QTY;i=i+1) begin : mapping_spi
			assign emg_ads1299_cs_w[i] = eeg_ads1299_spi_cs[i];
			assign emg_ads1299_sclk_w[i] = eeg_ads1299_spi_sclk[i/2];
			assign emg_ads1299_mosi_w[i] = eeg_ads1299_spi_mosi[i/2];
			assign emg_ads1299_start_w[i] = eeg_ads1299_start;
		end
	endgenerate

	generate
		for(i=0;i<EEG_ADS1299_SPI_QTY;i=i+1) begin : mapping_reg
			assign eeg_ads1299_drdy_n[i] = emg_ads1299_drdy_w[2*i];
		end
	endgenerate

    assign eeg_ads1299_spi_miso[0] = (~eeg_ads1299_spi_cs[0])? emg_ads1299_miso_w[0]:((~eeg_ads1299_spi_cs[1])? emg_ads1299_miso_w[1]:1'bZ);
    assign eeg_ads1299_spi_miso[1] = (~eeg_ads1299_spi_cs[2])? emg_ads1299_miso_w[2]:((~eeg_ads1299_spi_cs[3])? emg_ads1299_miso_w[3]:1'bZ);
    assign eeg_ads1299_spi_miso[2] = (~eeg_ads1299_spi_cs[4])? emg_ads1299_miso_w[4]:((~eeg_ads1299_spi_cs[5])? emg_ads1299_miso_w[5]:1'bZ);
    assign eeg_ads1299_spi_miso[3] = (~eeg_ads1299_spi_cs[6])? emg_ads1299_miso_w[6]:((~eeg_ads1299_spi_cs[7])? emg_ads1299_miso_w[7]:1'bZ);
	
	
endmodule