`timescale 1ns/1ps
 
module trans_distribute_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	parameter 		T_CLK 			= 20;		//ns
	parameter 		CHIPSET_QTY		=  4;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg								clk						;
	reg								rst_n					;
	
	reg		[32-1:0]				m_axi_trans_tdata		;
	reg								m_axi_trans_tlast		;
	wire							m_axi_trans_tready		;
	reg								m_axi_trans_tvalid		;
	
	wire	[32*CHIPSET_QTY-1:0]	axi_txd_tdata_array		;
	wire	[ 1*CHIPSET_QTY-1:0]	axi_txd_tlast_array		;
	wire	[ 1*CHIPSET_QTY-1:0]	axi_txd_tready_array	;
	wire	[ 1*CHIPSET_QTY-1:0]	axi_txd_tvalid_array	;
	
	wire	[32-1:0]	axi_txd_tdata[0:CHIPSET_QTY-1]		;
	wire				axi_txd_tlast[0:CHIPSET_QTY-1]		;
	reg					axi_txd_tready[0:CHIPSET_QTY-1]		;
	wire				axi_txd_tvalid[0:CHIPSET_QTY-1]		;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	trans_distribute# 
		(
			.CHIPSET_QTY			( CHIPSET_QTY			)
		)
	DUT
		(
			.clk					( clk					),
			.rst_n					( rst_n					),
			
			.s_axi_rx_tdata			( m_axi_trans_tdata		),
			.s_axi_rx_tlast			( m_axi_trans_tlast		),
			.s_axi_rx_tready		( m_axi_trans_tready	),
			.s_axi_rx_tvalid		( m_axi_trans_tvalid	),
			
			.m_axi_tx_tdata_array	( axi_txd_tdata_array	),
			.m_axi_tx_tlast_array	( axi_txd_tlast_array	),
			.m_axi_tx_tready_array	( axi_txd_tready_array	),
			.m_axi_tx_tvalid_array	( axi_txd_tvalid_array	)
		);
	
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		
		#100
		@ ( posedge clk );
		m_axi_trans_tdata		<= 1	;
		m_axi_trans_tdata[25:22]<= 1	;
		m_axi_trans_tlast		<= 1'b0	;
		m_axi_trans_tvalid		<= 1'b1	;
		@ ( posedge clk );
		while (~m_axi_trans_tready) @ ( posedge clk );
		m_axi_trans_tdata		<= 2	;
		m_axi_trans_tdata[25:22]<= 1	;
		m_axi_trans_tlast		<= 1'b0	;
		m_axi_trans_tvalid		<= 1'b1	;
		@ ( posedge clk );
		while (~m_axi_trans_tready) @ ( posedge clk );
		m_axi_trans_tdata		<= 3	;
		m_axi_trans_tdata[25:22]<= 1	;
		m_axi_trans_tlast		<= 1'b0	;
		m_axi_trans_tvalid		<= 1'b1	;
		@ ( posedge clk );
		while (~m_axi_trans_tready) @ ( posedge clk );
		m_axi_trans_tdata		<= 4	;
		m_axi_trans_tdata[25:22]<= 1	;
		m_axi_trans_tlast		<= 1'b1	;
		m_axi_trans_tvalid		<= 1'b1	;
		@ ( posedge clk );
		while (~m_axi_trans_tready) @ ( posedge clk );
		m_axi_trans_tdata		<= 32'h80000005	;
		m_axi_trans_tdata[27:24]<= 0	;
		m_axi_trans_tlast		<= 1'b1	;
		m_axi_trans_tvalid		<= 1'b1	;
		@ ( posedge clk );
		while (~m_axi_trans_tready) @ ( posedge clk );
		m_axi_trans_tdata		<= 32'hC0000006	;
		m_axi_trans_tdata[27:24]<= 2	;
		m_axi_trans_tlast		<= 1'b1	;
		m_axi_trans_tvalid		<= 1'b1	;
		@ ( posedge clk );
		while (~m_axi_trans_tready) @ ( posedge clk );
		m_axi_trans_tdata		<= 32'hC0000007	;
		m_axi_trans_tdata[27:24]<= 3	;
		m_axi_trans_tlast		<= 1'b1	;
		m_axi_trans_tvalid		<= 1'b1	;
		@ ( posedge clk );
		while (~m_axi_trans_tready) @ ( posedge clk );
		m_axi_trans_tlast		<= 1'b0	;
		m_axi_trans_tvalid		<= 1'b0	;
		
		
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk				<= 1'b0		;
			rst_n			<= 1'b0		;
			
			m_axi_trans_tdata	<= 0	;
			m_axi_trans_tlast	<= 1'b0	;
			m_axi_trans_tvalid	<= 1'b0	;
			
			axi_txd_tready[0]	<= 1	;
			axi_txd_tready[1]	<= 1	;
			axi_txd_tready[2]	<= 1	;
			axi_txd_tready[3]	<= 1	;
			
		end
	endtask	
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	genvar i;
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : pack
			assign axi_txd_tready_array[i] = axi_txd_tready[i];
		end
	endgenerate
	
	generate
		for(i=0;i<CHIPSET_QTY;i=i+1) begin : unpack
			assign axi_txd_tdata[i] = axi_txd_tdata_array[32*i+31 : 32*i];
			assign axi_txd_tlast[i] = axi_txd_tlast_array[i];
			assign axi_txd_tvalid[i] = axi_txd_tvalid_array[i];
		end
	endgenerate
	
	
endmodule