`timescale 1ns/1ps

module rhs2116_mod#
	(
		parameter	DATA_WIDTH		= 32		,
		parameter	WIRE_DELAY		= 11
	)
	(
		input						cs			,
		input						sclk		,
		input						mosi		,
		output	reg					miso
	);
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg								rst_n		;
	
	reg	[32 - 1:0]					serial_in	;
	reg	[ 8 - 1:0]					rx_cnt		;
	reg	[32 - 1:0]					rx_data		;
	
	reg	[16 - 1:0]					cnv_res_hg	;
	
	reg	[ 8 - 1:0]					tx_cnt		;
	reg	[32 - 1:0]					tx_data		;
	reg	[32 - 1:0]					tx_data_t	;
	
	//*****************************************************************************
	initial begin
		#100 rst_n = 0;
		#100 rst_n = 1;
		
	end
	
	//RX
	always @ ( posedge sclk or negedge rst_n or posedge cs ) begin
		if( !rst_n )
			rx_cnt <= 0;
		else if( cs )
			rx_cnt <= 0;
		else if ( rx_cnt != 8'hFF )
			rx_cnt <= rx_cnt + 1'b1;
	end
	
	always @ ( posedge sclk or negedge rst_n or negedge cs ) begin
		if( !rst_n )
			serial_in <= 0;
		else if( cs )
			serial_in <= 0;
		else
			serial_in <= {serial_in[30:0], mosi};
	end
	
	always @ ( rx_cnt ) begin
		if( rx_cnt == 32 )
			rx_data <= serial_in;
	end
	
	//data
	always @ ( negedge rst_n or posedge cs ) begin
		if( !rst_n ) begin
			cnv_res_hg <= 0;
			tx_data <= 0;
		end else if( rx_cnt == 32 ) begin
			case ( rx_data[31:30] )
				2'b00: begin
						tx_data <= {cnv_res_hg, 6'd0, cnv_res_hg[15:6]};
						cnv_res_hg <= cnv_res_hg + 1'b1;
					end
				2'b11:
					tx_data <= {16'h0000, 16'hFFFF};
				default:
					tx_data <= 32'hZZZZZZZZ;
			endcase
		end
	end
	
	always @ ( negedge rst_n or negedge cs ) begin
		if ( !rst_n )
			tx_data_t <= 0;
		else
			tx_data_t <= tx_data;
	end
	
	//TX
	always @ ( posedge sclk or negedge rst_n or posedge cs ) begin
		if( !rst_n )
			tx_cnt <= 8'd31;
		else if( cs )
			tx_cnt <= 8'd31;
		else if ( tx_cnt != 8'h0 )
			tx_cnt <= tx_cnt - 1'b1;
	end
	
	always @ ( negedge sclk or negedge rst_n or negedge cs ) begin
		if( !rst_n )
			miso <= 1'bX;
		else if( ~cs )
			#10 miso <= tx_data_t[tx_cnt];
		else
			#12 miso <= tx_data_t[tx_cnt];
	end
	
		
endmodule