Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May 7 15:05:29 MDT 2023 | Date : Sun Aug 4 13:41:46 2024 | Host : 840-5CG14025H4 running 64-bit major release (build 9200) | Command : report_drc -file c64pro_top_drc_opted.rpt -pb c64pro_top_drc_opted.pb -rpx c64pro_top_drc_opted.rpx | Design : c64pro_top | Device : xc7z010clg400-2 | Speed File : -2 | Design State : Synthesized --------------------------------------------------------------------------------------------------------------------------------------------- Report DRC Table of Contents ----------------- 1. REPORT SUMMARY 2. REPORT DETAILS 1. REPORT SUMMARY ----------------- Netlist: netlist Floorplan: design_1 Design limits: Ruledeck: default Max violations: Violations found: 25 +-----------+----------+----------------------------+------------+ | Rule | Severity | Description | Violations | +-----------+----------+----------------------------+------------+ | CHECK-3 | Warning | Report rule limit reached | 1 | | REQP-1839 | Warning | RAMB36 async control check | 20 | | REQP-1840 | Warning | RAMB18 async control check | 4 | +-----------+----------+----------------------------+------------+ 2. REPORT DETAILS ----------------- CHECK-3#1 Warning Report rule limit reached REQP-1839 rule limit reached: 20 violations have been found. Related violations: REQP-1839#1 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (u_pl_top/u_rhs2116_top/transmit_arrange[0].u_trans_arrange/s_axi_cmd_tready_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#2 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#3 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#4 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#5 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#6 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/is_end_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#7 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/recv_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#8 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[4] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#9 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#10 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#11 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#12 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#13 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/is_end_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#14 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[5] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/recv_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#15 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[0]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#16 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[1]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#17 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[2]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#18 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/chipset_reg[3]) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#19 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/is_end_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1839#20 Warning RAMB36 async control check The RAMB36E1 u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/WEBWE[6] (net: u_pl_top/u_rhs2116_top/u_trans_distribute/output_fifo[0].u_axis_data_fifo_if_recv/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_rhs2116_top/u_trans_distribute/recv_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1840#1 Warning RAMB18 async control check The RAMB18E1 u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg has an input control pin u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_double_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg/ENARDEN (net: u_pl_top/u_rhs2116_top/u_sine_wave_gen/u_dds_stim_16ch/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/aclken) which is driven by a register (u_pl_top/u_rhs2116_top/u_sine_wave_gen/aclken_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1840#2 Warning RAMB18 async control check The RAMB18E1 u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENARDEN (net: u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/wea[0]) which is driven by a register (u_pl_top/u_upload_top/u_upload_sort/m_axis_eegY_tvalid_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1840#3 Warning RAMB18 async control check The RAMB18E1 u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (u_pl_top/u_upload_top/u_upload_protocol_intan/s_axis_eeg_tready_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: REQP-1840#4 Warning RAMB18 async control check The RAMB18E1 u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg has an input control pin u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/ENBWREN (net: u_pl_top/u_upload_top/u_upload_sort/u_axis_data_fifo_w8_d128/inst/gen_fifo.xpm_fifo_axis_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/enb) which is driven by a register (u_pl_top/u_upload_top/u_upload_protocol_ql/s_axis_eeg_tready_reg) that has an active asychronous set or reset. This may cause corruption of the memory contents and/or read values when the set/reset is asserted and is not analyzed by the default static timing analysis. It is suggested to eliminate the use of a set/reset to registers driving this RAMB pin or else use a synchronous reset in which the assertion of the reset is timed by default. Related violations: