xilinx.com ipcache c2809637cf1fcef4 0 fifo_generator_32w_16d 100000000 32 0 0 false false false 0 0 Slave_Interface_Clock_Enable Common_Clock fifo_generator_32w_16d 64 false 4 false false 0 2 1022 1022 1022 1022 1022 1022 3 false false false false false false false false false Hard_ECC false false false false false false true false false true Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Data_FIFO Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM Common_Clock_Block_RAM 0 14 1023 1023 1023 1023 1023 1023 13 false false false 0 Native false false false false false false false false false false false false false false 32 16 1024 16 1024 16 1024 16 false 32 16 Embedded_Reg false false Active_High Active_High AXI4 Standard_FIFO No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Empty_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold No_Programmable_Full_Threshold READ_WRITE 0 1 false 4 Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered Fully_Registered true Synchronous_Reset false 1 0 0 1 1 4 false false Active_High Active_High true false false false false Active_High 0 false Active_High 1 false 4 false FIFO false false false false FIFO FIFO 2 2 false FIFO FIFO FIFO zynq xc7z010 clg400 VERILOG -2 c2809637cf1fcef4 $Change: 3895624 $ ca982dd9 132 IP_Unknown 8 TRUE . . 2023.1.1 GLOBAL