*** Running vivado with args -log dds_stim_16ch.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source dds_stim_16ch.tcl ****** Vivado v2023.1.1 (64-bit) **** SW Build 3900603 on Fri Jun 16 19:31:24 MDT 2023 **** IP Build 3900379 on Sat Jun 17 05:28:05 MDT 2023 **** SharedData Build 3899622 on Fri Jun 16 03:34:24 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source dds_stim_16ch.tcl -notrace create_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 1935.715 ; gain = 161.121 INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: dds_stim_16ch Command: synth_design -top dds_stim_16ch -part xc7z010clg400-2 -incremental_mode off -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Device 21-403] Loading part xc7z010clg400-2 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 15424 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:07 . Memory (MB): peak = 2770.199 ; gain = 415.875 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'dds_stim_16ch' [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:76] WARNING: [Synth 8-5640] Port 'debug_axi_pinc_in' is missing in component declaration [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:79] WARNING: [Synth 8-5640] Port 'debug_axi_poff_in' is missing in component declaration [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:79] WARNING: [Synth 8-5640] Port 'debug_axi_resync_in' is missing in component declaration [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:79] WARNING: [Synth 8-5640] Port 'debug_axi_chan_in' is missing in component declaration [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:79] WARNING: [Synth 8-5640] Port 'debug_core_nd' is missing in component declaration [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:79] WARNING: [Synth 8-5640] Port 'debug_phase' is missing in component declaration [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:79] WARNING: [Synth 8-5640] Port 'debug_phase_nd' is missing in component declaration [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:79] Parameter C_XDEVICEFAMILY bound to: zynq - type: string Parameter C_MODE_OF_OPERATION bound to: 0 - type: integer Parameter C_MODULUS bound to: 9 - type: integer Parameter C_ACCUMULATOR_WIDTH bound to: 32 - type: integer Parameter C_CHANNELS bound to: 16 - type: integer Parameter C_HAS_PHASE_OUT bound to: 1 - type: integer Parameter C_HAS_PHASEGEN bound to: 1 - type: integer Parameter C_HAS_SINCOS bound to: 1 - type: integer Parameter C_LATENCY bound to: 4 - type: integer Parameter C_MEM_TYPE bound to: 1 - type: integer Parameter C_NEGATIVE_COSINE bound to: 0 - type: integer Parameter C_NEGATIVE_SINE bound to: 0 - type: integer Parameter C_NOISE_SHAPING bound to: 0 - type: integer Parameter C_OUTPUTS_REQUIRED bound to: 0 - type: integer Parameter C_OUTPUT_FORM bound to: 0 - type: integer Parameter C_OUTPUT_WIDTH bound to: 9 - type: integer Parameter C_PHASE_ANGLE_WIDTH bound to: 9 - type: integer Parameter C_PHASE_INCREMENT bound to: 1 - type: integer Parameter C_PHASE_INCREMENT_VALUE bound to: 000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000,000111110111010100010000 - type: string Parameter C_RESYNC bound to: 0 - type: integer Parameter C_PHASE_OFFSET bound to: 1 - type: integer Parameter C_PHASE_OFFSET_VALUE bound to: 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 - type: string Parameter C_OPTIMISE_GOAL bound to: 0 - type: integer Parameter C_USE_DSP48 bound to: 0 - type: integer Parameter C_POR_MODE bound to: 0 - type: integer Parameter C_AMPLITUDE bound to: 0 - type: integer Parameter C_HAS_ACLKEN bound to: 1 - type: integer Parameter C_HAS_ARESETN bound to: 1 - type: integer Parameter C_HAS_TLAST bound to: 0 - type: integer Parameter C_HAS_TREADY bound to: 0 - type: integer Parameter C_HAS_S_PHASE bound to: 0 - type: integer Parameter C_S_PHASE_TDATA_WIDTH bound to: 1 - type: integer Parameter C_S_PHASE_HAS_TUSER bound to: 0 - type: integer Parameter C_S_PHASE_TUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_S_CONFIG bound to: 1 - type: integer Parameter C_S_CONFIG_SYNC_MODE bound to: 0 - type: integer Parameter C_S_CONFIG_TDATA_WIDTH bound to: 64 - type: integer Parameter C_HAS_M_DATA bound to: 1 - type: integer Parameter C_M_DATA_TDATA_WIDTH bound to: 16 - type: integer Parameter C_M_DATA_HAS_TUSER bound to: 0 - type: integer Parameter C_M_DATA_TUSER_WIDTH bound to: 1 - type: integer Parameter C_HAS_M_PHASE bound to: 1 - type: integer Parameter C_M_PHASE_TDATA_WIDTH bound to: 32 - type: integer Parameter C_M_PHASE_HAS_TUSER bound to: 0 - type: integer Parameter C_M_PHASE_TUSER_WIDTH bound to: 1 - type: integer Parameter C_DEBUG_INTERFACE bound to: 0 - type: integer Parameter C_CHAN_WIDTH bound to: 4 - type: integer INFO: [Synth 8-3491] module 'dds_compiler_v6_0_22' declared at 'd:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/hdl/dds_compiler_v6_0_vh_rfs.vhd:47308' bound to instance 'U0' of component 'dds_compiler_v6_0_22' [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:194] INFO: [Synth 8-256] done synthesizing module 'dds_stim_16ch' (0#1) [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/synth/dds_stim_16ch.vhd:76] WARNING: [Synth 8-7129] Port CLK in module xbip_pipe_v3_0_6_viv__parameterized30 is either unconnected or has no load WARNING: [Synth 8-7129] Port CE in module xbip_pipe_v3_0_6_viv__parameterized30 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized30 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized30 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized30 is either unconnected or has no load WARNING: [Synth 8-7129] Port CLK in module xbip_pipe_v3_0_6_viv__parameterized28 is either unconnected or has no load WARNING: [Synth 8-7129] Port CE in module xbip_pipe_v3_0_6_viv__parameterized28 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized28 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized28 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized28 is either unconnected or has no load WARNING: [Synth 8-7129] Port CLK in module xbip_pipe_v3_0_6_viv__parameterized26 is either unconnected or has no load WARNING: [Synth 8-7129] Port CE in module xbip_pipe_v3_0_6_viv__parameterized26 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized26 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized26 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized26 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module sin_cos is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized24 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized24 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized24 is either unconnected or has no load WARNING: [Synth 8-7129] Port CLK in module xbip_pipe_v3_0_6_viv__parameterized22 is either unconnected or has no load WARNING: [Synth 8-7129] Port CE in module xbip_pipe_v3_0_6_viv__parameterized22 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized22 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized22 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized22 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized20 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized20 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized20 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized18 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized18 is either unconnected or has no load WARNING: [Synth 8-7129] Port CLK in module xbip_pipe_v3_0_6_viv__parameterized16 is either unconnected or has no load WARNING: [Synth 8-7129] Port CE in module xbip_pipe_v3_0_6_viv__parameterized16 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized16 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized16 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized16 is either unconnected or has no load WARNING: [Synth 8-7129] Port CLK in module xbip_pipe_v3_0_6_viv__parameterized8 is either unconnected or has no load WARNING: [Synth 8-7129] Port CE in module xbip_pipe_v3_0_6_viv__parameterized8 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized8 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized8 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized8 is either unconnected or has no load WARNING: [Synth 8-7129] Port SCLR in module xbip_pipe_v3_0_6_viv__parameterized14 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized14 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized14 is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized12 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized12 is either unconnected or has no load WARNING: [Synth 8-7129] Port chan_addr_del3[3] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port chan_addr_del3[2] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port chan_addr_del3[1] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port chan_addr_del3[0] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[3] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[2] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[1] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port addr_i[0] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port phase_inc_we in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port phase_adj_we in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[31] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[30] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[29] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[28] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[27] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[26] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[25] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[24] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[23] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[22] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[21] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[20] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[19] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[18] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[17] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[16] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[15] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[14] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[13] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[12] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[11] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[10] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[9] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[8] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[7] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[6] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[5] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[4] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[3] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[2] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[1] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port data_i[0] in module accum is either unconnected or has no load WARNING: [Synth 8-7129] Port SSET in module xbip_pipe_v3_0_6_viv__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port SINIT in module xbip_pipe_v3_0_6_viv__parameterized10 is either unconnected or has no load WARNING: [Synth 8-7129] Port RFD in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port CHANNEL[3] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port CHANNEL[2] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port CHANNEL[1] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port CHANNEL[0] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port COSINE[8] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port COSINE[7] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port COSINE[6] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port COSINE[5] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port COSINE[4] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port COSINE[3] in module dds_compiler_v6_0_22_core is either unconnected or has no load WARNING: [Synth 8-7129] Port COSINE[2] in module dds_compiler_v6_0_22_core is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 2932.801 ; gain = 578.477 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 2950.723 ; gain = 596.398 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:11 . Memory (MB): peak = 2950.723 ; gain = 596.398 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.024 . Memory (MB): peak = 2962.773 ; gain = 0.000 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc] for cell 'U0' Finished Parsing XDC File [d:/wlb_files/VivadoPrj/c64_pro/c64_pro.gen/sources_1/ip/dds_stim_16ch/dds_stim_16ch_ooc.xdc] for cell 'U0' Parsing XDC File [D:/wlb_files/VivadoPrj/c64_pro/c64_pro.runs/dds_stim_16ch_synth_1/dont_touch.xdc] Finished Parsing XDC File [D:/wlb_files/VivadoPrj/c64_pro/c64_pro.runs/dds_stim_16ch_synth_1/dont_touch.xdc] Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3063.406 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.042 . Memory (MB): peak = 3063.406 ; gain = 0.000 INFO: [Designutils 20-5008] Incremental synthesis strategy off --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:10 ; elapsed = 00:00:19 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-2 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:10 ; elapsed = 00:00:19 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property KEEP_HIERARCHY = SOFT for U0. (constraint file D:/wlb_files/VivadoPrj/c64_pro/c64_pro.runs/dds_stim_16ch_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:10 ; elapsed = 00:00:19 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:19 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 80 (col length:40) BRAMs: 120 (col length: RAMB18 40 RAMB36 20) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:11 ; elapsed = 00:00:21 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:26 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+---------+------+ | |Cell |Count | +------+---------+------+ |1 |CARRY4 | 18| |2 |LUT1 | 6| |3 |LUT2 | 70| |4 |LUT3 | 5| |5 |LUT4 | 12| |6 |LUT5 | 2| |7 |LUT6 | 1| |8 |RAM32M | 17| |9 |RAMB18E1 | 1| |10 |FDRE | 231| |11 |FDSE | 10| +------+---------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 11 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:08 ; elapsed = 00:00:27 . Memory (MB): peak = 3063.406 ; gain = 596.398 Synthesis Optimization Complete : Time (s): cpu = 00:00:16 ; elapsed = 00:00:29 . Memory (MB): peak = 3063.406 ; gain = 709.082 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 3063.406 ; gain = 0.000 INFO: [Netlist 29-17] Analyzing 36 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 3063.406 ; gain = 0.000 INFO: [Project 1-111] Unisim Transformation Summary: A total of 17 instances were transformed. RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 17 instances Synth Design complete | Checksum: 90e24062 INFO: [Common 17-83] Releasing license: Synthesis 20 Infos, 108 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:17 ; elapsed = 00:00:45 . Memory (MB): peak = 3063.406 ; gain = 1088.645 INFO: [Common 17-1381] The checkpoint 'D:/wlb_files/VivadoPrj/c64_pro/c64_pro.runs/dds_stim_16ch_synth_1/dds_stim_16ch.dcp' has been generated. INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP dds_stim_16ch, cache-ID = 6293a64780c6107c INFO: [Coretcl 2-1174] Renamed 23 cell refs. INFO: [Common 17-1381] The checkpoint 'D:/wlb_files/VivadoPrj/c64_pro/c64_pro.runs/dds_stim_16ch_synth_1/dds_stim_16ch.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file dds_stim_16ch_utilization_synth.rpt -pb dds_stim_16ch_utilization_synth.pb INFO: [Common 17-206] Exiting Vivado at Thu Aug 17 17:22:28 2023...