`timescale 1 ns / 1 ps

module pwm_gen#
	(
		parameter	DATA_WIDTH			= 10
	)
	(
		input							clk			,
		input							rst_n		,
		
		input							enable		,
		input		[DATA_WIDTH-1:0]	period		,
		input		[DATA_WIDTH-1:0]	duty		,
        
		output	reg						pwm
	);
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg [DATA_WIDTH-1:0]	max				;
	reg [DATA_WIDTH-1:0]	cnt				;
	
	//*****************************************************************************
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			max <= 0;
		else if ( cnt == 0 )
			max <= period;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			cnt <= 0;
		else if ( ~enable )
			cnt <= 0;
		else if ( cnt != max )
			cnt <= cnt + 1'b1;
		else
			cnt <= 0;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			pwm <= 1'b0;
		else if ( cnt == duty )
			pwm <= 1'b0;
		else if ( enable && cnt == 0 )
			pwm <= 1'b1;
	end
	
endmodule