`timescale 1ns/1ps
 
module led_ctrl_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	localparam	T_CLK 			= 10;		//ns

	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg								clk					;
	reg								rst_n				;
	
	reg		[3-1:0]					cmd					;
	wire							led					;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	led_ctrl#
		(
			.CLK_PERIOD			( T_CLK			        )
		)
	DUT
		(
			.clk				( clk					),
			.rst_n				( rst_n					),
			
			.cmd				( cmd					),
			.led				( led					)
		);
	
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		#100;

		cmd	<= 3'b011;

	//	#40_000
	//	@ ( posedge clk );
	//	$stop;
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk		<= 1'b0	;
			rst_n	<= 1'b0	;
			
			cmd		<= 3'b000;
			
		end
	endtask
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
    

endmodule