`timescale 1 ns / 1 ps

module emg_top#
	(
		parameter		CLK_PERIOD			= 10			,

		parameter		SPI_CLK_DIV			= 5				,
		parameter		CHIPSET_QTY		    = 1				,
		parameter		SPI_TRANS_PERIOD    = 2000
	)
	(
		input							clk					,
		input							rst_n				,
		
		input	[13-1:0]				bram_addr			,
		input							bram_clk			,
		input	[32-1:0]				bram_din			,
		output	[32-1:0]				bram_dout			,
		input							bram_en				,
		input							bram_rst			,
		input	[ 4-1:0]				bram_we				,

		output							interrupt			,
		
        //------------------------------------------ FIFO: emg output
		output	[32-1:0]				axis_txd_tdata	    ,
		output							axis_txd_tlast	    ,
		input							axis_txd_tready	    ,
		output							axis_txd_tvalid	    ,
	
		//------------------------------------------ device interface
		output	                		cs					,
		output	                		sclk				,
		output	                		mosi				,
		input	                		miso				,
		input	                		drdy				,
		output							start				,
		output							reset_n				,
		output							pwdn_n
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Procedural blocks
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	assign bram_dout = 0;
	assign interrupt = 1'b0;
	assign axis_txd_tdata = 0;
	assign axis_txd_tlast = 1'b0;
	assign axis_txd_tvalid = 1'b0;
	assign cs = 1'b0;
	assign sclk = 1'b0;
	assign mosi = 1'b0;
	assign start = 1'b0;
	assign reset_n = 1'b1;
	assign pwdn_n = 1'b1;
	
endmodule