xilinx.com ipcache 97d99f7b2416eb51 0 dds_stim_16ch 100000000 100000000 100000000 100000000 Full_Range 16 dds_stim_16ch Not_Required 50 Minimal 0.4 Coregen true true true false 4 Auto Not_Required Not_Required Auto Standard 9 false false None Twos_Complement Auto 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Sine 9 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0001010011111001 0 0 0 0 0 0 0 0 010000000000000000000000 100000000000000000000000 110000000000000000000000 0 0 0 0 0 false Hardware_Parameters Phase_Generator_and_SIN_COS_LUT Programmable 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 Programmable false On_Vector Not_Required 1 45 false 1 zynq xc7z010 clg400 VERILOG -2 97d99f7b2416eb51 $Change: 3895624 $ 9b073c73 116 IP_Unknown 22 TRUE . . 2023.1.1 GLOBAL