`timescale 1 ns / 1 ps

module run_time#
	(
		parameter	CLK_PERIOD			= 10
	)
	(
		input							clk			,
		input							rst_n		,
        
		output	reg						pulse_ms	,
		output	reg	[64-1:0]			run_time_ms
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	CLKS_OF_MS	= 1000000/CLK_PERIOD;
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg		[20-1:0]	cnt_clk				;
	
	//*****************************************************************************
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			cnt_clk <= 0;
		else if ( cnt_clk == CLKS_OF_MS - 1 )
			cnt_clk <= 0;
		else
			cnt_clk <= cnt_clk + 1'b1;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			pulse_ms <= 1'b0;
		else if ( cnt_clk == CLKS_OF_MS - 1 )
			pulse_ms <= 1'b1;
		else
			pulse_ms <= 1'b0;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			run_time_ms <= 0;
		else if ( pulse_ms )
			run_time_ms <= run_time_ms + 1'b1;
	end
	
endmodule