`timescale 1ns/1ps
 
module trans_arrange_tb();

	//*****************************************************************************
	// Parameter definition
	//*****************************************************************************
	parameter	T_CLK 				= 20;	//ns
	parameter	SPI_TRANS_PERIOD	= 1500;	//ns
	
	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg							clk					;
	reg							rst_n				;
	
	reg		[32-1:0]			update_period		;
	
	reg							enable_timer		;
	wire						trans_round   		;
	wire						trans_pulse   		;
	
	reg							dds_enable			;
	reg							dds_reset_n			;
	
	reg							phase_enable		;
	reg		[32-1:0]			phase_inc[0:16-1]	;
	reg		[32-1:0]			phase_off[0:16-1]	;
	wire	[24*16-1:0]			phase_inc_array		;
	wire	[24*16-1:0]			phase_off_array		;
	
	reg		[   32-1:0]			cnv_cmd[0:16-1]		;
	wire	[16*32-1:0]			cnv_cmd_array		;
	reg		[    8-1:0]			cnv_cmd_lth			;
	reg		[    8-1:0]			cnv_divisor			;
	reg		[16* 8-1:0]			stim_trim_p_array	;
	reg		[16* 8-1:0]			stim_trim_n_array	;
	
	reg							enable_record		;
	reg							enable_stim			;
	
	wire	[16* 9-1:0]			sine_wave_array		;
	
	reg		[32-1:0]			m_axi_stim_tdata	;
	reg							m_axi_stim_tlast	;
	wire						m_axi_stim_tready	;
	reg							m_axi_stim_tvalid	;
	
	wire						m_axis_tvalid   	;
	wire						m_axis_tready   	;
	wire	[32-1:0]			m_axis_tdata   		;
	wire						m_axis_tlast   		;
	
	wire	[32-1:0]			s_axi_trans_tdata	;
	wire						s_axi_trans_tlast	;
	reg							s_axi_trans_tready	;
	wire						s_axi_trans_tvalid	;
	
	integer	n;
	
	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	axis_data_fifo_w32_d32 u_axis_data_fifo_w32_d32
		(
			.s_axis_aclk			( clk 					),
			.s_axis_aresetn			( 1'b1					),
			
			.s_axis_tvalid			( m_axi_stim_tvalid		),
			.s_axis_tready			( m_axi_stim_tready		),
			.s_axis_tdata			( m_axi_stim_tdata		),
			.s_axis_tlast			( m_axi_stim_tlast		),
			
			.m_axis_tvalid			( m_axis_tvalid   		),
			.m_axis_tready			( m_axis_tready   		),
			.m_axis_tdata			( m_axis_tdata   		),
			.m_axis_tlast			( m_axis_tlast   		)
		);
		
	trans_timer# 
		(
			.CLK_PERIOD				( T_CLK					),
			.SPI_TRANS_PERIOD		( SPI_TRANS_PERIOD		)
		)
	u_trans_timer
		(
			.clk					( clk					),
			.rst_n					( rst_n					),
			
			.enable					( enable_timer			),
			.update_period			( update_period			),
			
			.update					( trans_round			),
			.trans					( trans_pulse			)
		);
	
	sine_gen u_sine_wave_gen
		(
			.clk					( clk					),
			.rst_n					( rst_n					),
			
			.aclken					( dds_enable			),
			.aresetn				( dds_reset_n			),
			
			.phase_enable			( phase_enable			),
			.phase_inc_array		( phase_inc_array		),
			.phase_off_array		( phase_off_array		),
			
			.update					( trans_round			),
			.sine_wave_array		( sine_wave_array		)
		);
	
	trans_arrange# 
		(
			.REG_ADDR_MONITOR		( 8'd40					),
			.REG_ADDR_STIM_POL		( 8'd44					),
			.REG_ADDR_POS_CUR		( 8'd64					),
			.REG_ADDR_NEG_CUR		( 8'd96					)
		)
	DUT
		(
			.clk					( clk					),
			.rst_n					( rst_n					),
			
			.cnv_cmd_array			( cnv_cmd_array			),
			.cnv_cmd_lth			( cnv_cmd_lth			),
			.cnv_divisor			( cnv_divisor			),	//<8>
			.stim_trim_p			( stim_trim_p_array		),	//<8*16>
			.stim_trim_n			( stim_trim_n_array		),	//<8*16>
			
			.enable_record			( enable_record			),
			.enable_stim			( enable_stim			),
			.trans_round			( trans_round			), 
			
			//--------------------------------------------------From DDS
			.sine_wave_array		( sine_wave_array		),	//<9*16>
			
			//--------------------------------------------------From PS
			.s_axi_stim_tdata		( m_axis_tdata			),
			.s_axi_stim_tlast		( m_axis_tlast			),
			.s_axi_stim_tready		( m_axis_tready			),
			.s_axi_stim_tvalid		( m_axis_tvalid			),
			
			//--------------------------------------------------To trans_distribute
			.m_axi_trans_tdata		( s_axi_trans_tdata		),
			.m_axi_trans_tlast		( s_axi_trans_tlast		),
			.m_axi_trans_tready		( s_axi_trans_tready	),
			.m_axi_trans_tvalid		( s_axi_trans_tvalid	)
		);
	
	//*****************************************************************************
	always #( T_CLK/2.0 )  clk = !clk;
	
	initial begin
		Initial();
		#100 rst_n = 0;
		#100 rst_n = 1;
		
		#100
		@ ( posedge clk );
		m_axi_stim_tdata[31:30]	<= 2'b00;	//need fill
		m_axi_stim_tdata[29:24] <= 0;
		m_axi_stim_tdata[23:16] <= 5;		//stim ch
		m_axi_stim_tdata[15: 9] <= 0;		//sine ch
		m_axi_stim_tdata[ 8: 0] <= 9'h000;	//gain_c
		
		m_axi_stim_tvalid	<= 1'b1;
		m_axi_stim_tlast	<= 1'b0;
		
		@ ( posedge clk );
		while (~m_axi_stim_tready) @ ( posedge clk );
		m_axi_stim_tdata[31:30]	<= 2'b00;	//need fill
		m_axi_stim_tdata[29:24] <= 0;
		m_axi_stim_tdata[23:16] <= 6;		//stim ch
		m_axi_stim_tdata[15: 9] <= 1;		//sine ch
		m_axi_stim_tdata[ 8: 0] <= 9'h100;	//gain_c
		
		@ ( posedge clk );
		while (~m_axi_stim_tready) @ ( posedge clk );
		m_axi_stim_tdata[31:30]	<= 2'b10;	//un fill
		m_axi_stim_tdata[29:24] <= 0;
		m_axi_stim_tdata[23:16] <= 64+7;	//write reg
		m_axi_stim_tdata[15: 8] <= 0;		//trim
		m_axi_stim_tdata[ 7: 0] <= 8'h78;	//magnitude
		
		@ ( posedge clk );
		while (~m_axi_stim_tready) @ ( posedge clk );
		m_axi_stim_tdata[31:30]	<= 2'b10;		//un fill
		m_axi_stim_tdata[29:24] <= 0;
		m_axi_stim_tdata[23:16] <= 44;			//write reg
		m_axi_stim_tdata[15: 0] <= 16'h0001<<7;	//polarity
		
		m_axi_stim_tlast	<= 1'b1;
		@ ( posedge clk );
		while (~m_axi_stim_tready) @ ( posedge clk );
		m_axi_stim_tvalid	<= 1'b0;
		m_axi_stim_tlast	<= 1'b0;
		
		#100
		@ ( posedge clk );
		dds_enable		<= 1'b1;
		dds_reset_n		<= 1'b1;
		enable_record	<= 1'b1;
		enable_stim		<= 1'b1;
		enable_timer	<= 1'b1;
		
		for(n=1;n<10;n=n+1) begin
			#100
			@ ( posedge clk );
			m_axi_stim_tdata[31:30]	<= 2'b00;	//need fill
			m_axi_stim_tdata[29:24] <= 0;
			m_axi_stim_tdata[23:16] <= 5;		//stim ch
			m_axi_stim_tdata[15: 9] <= 0;		//sine ch
			m_axi_stim_tdata[ 8: 0] <= 9'h000;	//gain_c
			
			m_axi_stim_tvalid	<= 1'b1;
			m_axi_stim_tlast	<= 1'b0;
			
			@ ( posedge clk );
			while (~m_axi_stim_tready) @ ( posedge clk );
			m_axi_stim_tdata[31:30]	<= 2'b00;	//need fill
			m_axi_stim_tdata[29:24] <= 0;
			m_axi_stim_tdata[23:16] <= 6;		//stim ch
			m_axi_stim_tdata[15: 9] <= 1;		//sine ch
			m_axi_stim_tdata[ 8: 0] <= 9'h100;	//gain_c
			
			@ ( posedge clk );
			while (~m_axi_stim_tready) @ ( posedge clk );
			m_axi_stim_tdata[31:30]	<= 2'b10;	//un fill
			m_axi_stim_tdata[29:24] <= 0;
			m_axi_stim_tdata[23:16] <= 64+7;	//write reg
			m_axi_stim_tdata[15: 8] <= 0;		//trim
			m_axi_stim_tdata[ 7: 0] <= 8'h79;	//magnitude
			
			@ ( posedge clk );
			while (~m_axi_stim_tready) @ ( posedge clk );
			m_axi_stim_tdata[31:30]	<= 2'b10;		//un fill
			m_axi_stim_tdata[29:24] <= 0;
			m_axi_stim_tdata[23:16] <= 44;			//write reg
			m_axi_stim_tdata[15: 0] <= 16'h0001<<7;	//polarity
			
			m_axi_stim_tlast	<= 1'b1;
			@ ( posedge clk );
			while (~m_axi_stim_tready) @ ( posedge clk );
			m_axi_stim_tvalid	<= 1'b0;
			m_axi_stim_tlast	<= 1'b0;
		end
		
		
	end
	
	//*****************************************************************************
	// Task
	//*****************************************************************************
	task Initial;
		begin
			clk				<= 1'b0			;
			rst_n			<= 1'b0			;
			
			update_period	<= (SPI_TRANS_PERIOD*7)/T_CLK;
			
			cnv_cmd_lth <= 3;
			cnv_cmd[ 0]	<= 32'h00010000;
			cnv_cmd[ 1]	<= 32'h00020000;
			cnv_cmd[ 2]	<= 32'h00030000;
			cnv_cmd[ 3]	<= 32'h00000000;
			cnv_cmd[ 4]	<= 32'h00000000;
			cnv_cmd[ 5]	<= 32'h00000000;
			cnv_cmd[ 6]	<= 32'h00000000;
			cnv_cmd[ 7]	<= 32'h00000000;
			cnv_cmd[ 8]	<= 32'h00000000;
			cnv_cmd[ 9]	<= 32'h00000000;
			cnv_cmd[10]	<= 32'h00000000;
			cnv_cmd[11]	<= 32'h00000000;
			cnv_cmd[12]	<= 32'h00000000;
			cnv_cmd[13]	<= 32'h00000000;
			cnv_cmd[14]	<= 32'h00000000;
			cnv_cmd[15]	<= 32'h00000000;
			
			cnv_divisor	<= 0;
			stim_trim_p_array <= 0;
			stim_trim_n_array <= 0;
			
			phase_enable	<= 1'b0;
			phase_inc[ 0] 	<= 0;
			phase_inc[ 1] 	<= 0;
			phase_inc[ 2] 	<= 0;
			phase_inc[ 3] 	<= 0;
			phase_inc[ 4] 	<= 0;
			phase_inc[ 5] 	<= 0;
			phase_inc[ 6] 	<= 0;
			phase_inc[ 7] 	<= 0;
			phase_inc[ 8] 	<= 0;
			phase_inc[ 9] 	<= 0;
			phase_inc[10] 	<= 0;
			phase_inc[11] 	<= 0;
			phase_inc[12] 	<= 0;
			phase_inc[13] 	<= 0;
			phase_inc[14] 	<= 0;
			phase_inc[15] 	<= 0;
			
			phase_off[ 0] 	<= 0;
			phase_off[ 1] 	<= 0;
			phase_off[ 2] 	<= 0;
			phase_off[ 3] 	<= 0;
			phase_off[ 4] 	<= 0;
			phase_off[ 5] 	<= 0;
			phase_off[ 6] 	<= 0;
			phase_off[ 7] 	<= 0;
			phase_off[ 8] 	<= 0;
			phase_off[ 9] 	<= 0;
			phase_off[10] 	<= 0;
			phase_off[11] 	<= 0;
			phase_off[12] 	<= 0;
			phase_off[13] 	<= 0;
			phase_off[14] 	<= 0;
			phase_off[15] 	<= 0;
			
			dds_enable		<= 1'b0;
			dds_reset_n		<= 1'b0;
	
			enable_record	<= 1'b0;
			enable_stim		<= 1'b0;
			
			enable_timer	<= 1'b0;
			
			s_axi_trans_tready	<= 1'b1;
	
			m_axi_stim_tdata	<= 0;
			m_axi_stim_tlast	<= 1'b0;
			m_axi_stim_tvalid	<= 1'b0;
			
		end
	endtask
	
	//*****************************************************************************
	// Wire assignment
	//*****************************************************************************
	genvar i;
	
	generate
		for(i=0;i<16;i=i+1) begin : pack
			assign phase_inc_array[24*i+23 : 24*i] = phase_inc[i];
			assign phase_off_array[24*i+23 : 24*i] = phase_off[i];
			assign cnv_cmd_array[32*i+31 : 32*i] = cnv_cmd[i];
		end
	endgenerate
	
endmodule