`timescale 1 ns / 1 ps

module upload_config#
	(
		parameter	CHANNLE_QTY			= 64	,
		parameter	PRE_MSG_LEN			= 24
	)
	(
		input								clk					,
		input								rst_n				,
		
		input		[13-1:0]				bram_addr			,
		input								bram_clk			,
		input		[32-1:0]				bram_din			,
		output	reg	[32-1:0]				bram_dout			,
		input								bram_en				,
		input								bram_rst			,
		input		[ 4-1:0]				bram_we				,

		output	reg							eeg_sel				,
		output	reg							protocol_sel		,
		output		[ 8*PRE_MSG_LEN-1:0]	pre_message_array	,
		output		[ 8*CHANNLE_QTY-1:0]	ch_mapping2pc_array	,
		output		[   CHANNLE_QTY-1:0]	upload_ch_array		,
		output	reg	[32-1:0]				upload_round_qty_set,
		output	reg	[ 8-1:0]				pre_message_length	,
		output	reg							reset_package_id	,
		output	reg	[32-1:0]				package_overtime_ms
	);
	
	//*****************************************************************************
	// localparam definition
	//*****************************************************************************
	localparam 	BRAM_ADDR_TEST_RO				= 13'h0000;
	localparam 	BRAM_ADDR_TEST_RW				= 13'h0004;
	
	localparam 	BRAM_ADDR_SEL					= 13'h0010;
	localparam 	BRAM_ADDR_ROUNDS_QTY			= 13'h0014;
	localparam 	BRAM_ADDR_PRE_MSG_LTH			= 13'h0018;
	localparam 	BRAM_ADDR_RESET_PACKAGE_ID		= 13'h001C;
	localparam 	BRAM_ADDR_PACKAGE_OVERTIME		= 13'h0020;
	localparam 	BRAM_ADDR_MESSAGE_END			= 13'h0024;

	localparam 	BRAM_ADDR_PRE_MSG_START			= 13'h0100;
	localparam 	BRAM_ADDR_PRE_MSG_MASK			= 13'h1F00;

	localparam 	BRAM_ADDR_CH_MAP_START			= 13'h0200;
	localparam 	BRAM_ADDR_CH_MAP_MASK			= 13'h1F00;

	localparam 	BRAM_ADDR_UPLOAD_CH_START		= 13'h0300;
	localparam 	BRAM_ADDR_UPLOAD_CH_MASK		= 13'h1F00;
	
	localparam 	N		= (CHANNLE_QTY+7)/8;

	//*****************************************************************************
	// Internal register and wire declarations
	//*****************************************************************************
	reg		[32-1:0]		test_data						;
	
	wire					bram_wr_valid					;
	wire					bram_rd_valid					;

	reg		[ 8-1:0]		pre_message[0:PRE_MSG_LEN-1]	;
	reg		[ 8-1:0]		ch_mapping2pc[0:CHANNLE_QTY-1]	;
	reg		[ 8-1:0]		upload_ch[0:N-1]				;
	wire	[8*N-1:0]		upload_ch_array_w				;

	integer	n;
	
	genvar i;

	//*****************************************************************************
	// Instantiation
	//*****************************************************************************
	
	
	//*****************************************************************************
	// Procedural blocks
	//*****************************************************************************

	//write bram/Set config
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			test_data <= 0;
		else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_TEST_RW ) )
			test_data <= bram_din;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if ( !rst_n ) begin
			eeg_sel <= 1'b0;
			protocol_sel <= 1'b0;
		end else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_SEL ) ) begin
			eeg_sel <= bram_din[0];
			protocol_sel <= bram_din[1];
		end
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			upload_round_qty_set <= 0;
		else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_ROUNDS_QTY ) )
			upload_round_qty_set <= bram_din;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			pre_message_length <= 0;
		else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_PRE_MSG_LTH ) )
			pre_message_length <= bram_din[7:0];
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			reset_package_id <= 1'b0;
		else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_RESET_PACKAGE_ID ) )
			reset_package_id <= 1'b1;
		else
			reset_package_id <= 1'b0;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n )
			package_overtime_ms <= 10;
		else if ( bram_wr_valid && ( bram_addr == BRAM_ADDR_PACKAGE_OVERTIME ) )
			package_overtime_ms <= bram_din;
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			for(n=0; n<PRE_MSG_LEN; n=n+1) begin
				pre_message[n] <= 0;
			end
		end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_PRE_MSG_MASK) == BRAM_ADDR_PRE_MSG_START ) ) begin
			pre_message[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:pre_message[{bram_addr[7:2],2'b00}];
			pre_message[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:pre_message[{bram_addr[7:2],2'b01}];
			pre_message[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:pre_message[{bram_addr[7:2],2'b10}];
			pre_message[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:pre_message[{bram_addr[7:2],2'b11}];
		end
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			for(n=0; n<CHANNLE_QTY; n=n+1) begin
				ch_mapping2pc[n] <= 0;
			end
		end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_CH_MAP_MASK) == BRAM_ADDR_CH_MAP_START ) ) begin
			ch_mapping2pc[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:ch_mapping2pc[{bram_addr[7:2],2'b00}];
			ch_mapping2pc[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:ch_mapping2pc[{bram_addr[7:2],2'b01}];
			ch_mapping2pc[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:ch_mapping2pc[{bram_addr[7:2],2'b10}];
			ch_mapping2pc[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:ch_mapping2pc[{bram_addr[7:2],2'b11}];
		end
	end
	
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			for(n=0; n<N; n=n+1) begin
				upload_ch[n] <= 0;
			end
		end else if ( bram_wr_valid && ( (bram_addr & BRAM_ADDR_UPLOAD_CH_MASK) == BRAM_ADDR_UPLOAD_CH_START ) ) begin
			upload_ch[{bram_addr[7:2],2'b00}] <= (bram_we[0])? bram_din[ 7: 0]:upload_ch[{bram_addr[7:2],2'b00}];
			upload_ch[{bram_addr[7:2],2'b01}] <= (bram_we[1])? bram_din[15: 8]:upload_ch[{bram_addr[7:2],2'b01}];
			upload_ch[{bram_addr[7:2],2'b10}] <= (bram_we[2])? bram_din[23:16]:upload_ch[{bram_addr[7:2],2'b10}];
			upload_ch[{bram_addr[7:2],2'b11}] <= (bram_we[3])? bram_din[31:24]:upload_ch[{bram_addr[7:2],2'b11}];
		end
	end
	
	//read bram/Get config
	always @ ( posedge clk or negedge rst_n ) begin
		if( !rst_n ) begin
			bram_dout <= 0;
		end else if ( bram_rd_valid ) begin
			
			if ( bram_addr == BRAM_ADDR_TEST_RO )
				bram_dout <= 32'h12340004;

			if ( bram_addr == BRAM_ADDR_TEST_RW )
				bram_dout <= test_data;
			
		end
	end
	
	//*****************************************************************************
	// Continuous assignments
	//*****************************************************************************
	assign bram_wr_valid = bram_en && (bram_we != 4'h0);
	assign bram_rd_valid = bram_en && (bram_we == 4'h0);

	generate
		for(i=0;i<PRE_MSG_LEN;i=i+1) begin : pack_pre_msg
			assign pre_message_array[8*i+7 : 8*i] = pre_message[i];
		end
	endgenerate

	generate
		for(i=0;i<CHANNLE_QTY;i=i+1) begin : pack_ch_mapping
			assign ch_mapping2pc_array[8*i+7 : 8*i] = ch_mapping2pc[i];
		end
	endgenerate

	generate
		for(i=0;i<N;i=i+1) begin : pack_upload_channel
			assign upload_ch_array_w[8*i+7 : 8*i] = upload_ch[i];
		end
	endgenerate

	generate
		for(i=0;i<CHANNLE_QTY;i=i+1) begin : link_upload_channel
			assign upload_ch_array[i] = upload_ch_array_w[i];
		end
	endgenerate
	
endmodule